View W89C841D_5963944.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

w89c841f /d 3 - in - 1 10 /10 0m fast ethernet controller publication release date: october 1 8 , 2001 - 1 - revision a 3 w89c841f /d 3 - in - 1 100 base - tx/fx & 10base - t ethernet controller
w 89c841f /d - 2 - the information described in this document is the exclusive intellectual property of winbond electronics corporation and shall not be reproduced without permiss ion from winbond. winbond is providing this document only for reference purposes of w89c841f - based system design. winbond assumes no responsibility for errors or omissions. all data and specifications are subject to change without notice. pc, at and ibm ar e registered trademarks of international business machines, inc. dos and windows are registered trademarks of microsoft corporation. all other trademarks mentioned in this document are property of their respective owners. for additional information or qu estions, please contact: winbond electronics corp.
w89c841f /d pub lication release date: october 1 8 , 2001 - 3 - revision a3 table of contents - 1. general descripti on ................................ ................................ ................................ .......................... 4 2. features ................................ ................................ ................................ ................................ ................. 4 3. pin configuration s ................................ ................................ ................................ ............................. 6 4. pin description ................................ ................................ ................................ ................................ ..... 9 pci interface ................................ ................................ ................................ ................................ .............. 9 power management interface ................................ ................................ ................................ ................. 14 bootrom/flash and eeprom interface ................................ ................................ ................................ 15 transceiver interface ................................ ................................ ................................ ............................... 19 led interface ................................ ................................ ................................ ................................ ........... 20 configuration and test interface ................................ ................................ ................................ ............. 20 power pins ................................ ................................ ................................ ................................ .............. 20 5. block diagram ................................ ................................ ................................ ................................ .... 23 6. system diagram ................................ ................................ ................................ ................................ .. 24 7. functional descri p tion ................................ ................................ ................................ .................. 25 operation mode configuration ................................ ................................ ................................ ................ 25 direct memory access function ................................ ................................ ................................ .............. 25 media access control (mac) function ................................ ................................ ................................ ... 26 full duplex and half duplex function ................................ ................................ ................................ ..... 26 network media speed function ................................ ................................ ................................ .............. 26 flow control in full duplex mode ................................ ................................ ................................ ............ 26 priority tagged frame supporting qos ................................ ................................ ................................ .. 26 eeprom auto - load and software programming function ................................ ................................ ..... 27 bootrom read and flash programming function ................................ ................................ ................. 30 mii management function ................................ ................................ ................................ ....................... 32 system resource configuring ................................ ................................ ................................ ................. 32 power management function ................................ ................................ ................................ .................. 33 8. configuration reg isters ................................ ................................ ................................ .............. 33 configuration register mapping ................................ ................................ ................................ .............. 34 9. function register s ................................ ................................ ................................ .......................... 47 cxx function registers ................................ ................................ ................................ ........................... 47 dxx function registers ................................ ................................ ................................ ........................... 62 mii management registers ................................ ................................ ................................ ..................... 79 10. electrical chara cteristics ................................ ................................ ................................ ....... 90 absolute maximum ratings ................................ ................................ ................................ ..................... 90 power supply ................................ ................................ ................................ ................................ .......... 90 dc characteristics ................................ ................................ ................................ ................................ ... 90 ac characteristics ................................ ................................ ................................ ................................ ... 91 11. package dimensio ns ................................ ................................ ................................ ..................... 1 00 w89c841f: 128l qfp (14 x 20 x 2.75 mm footprint 3.2 mm) ................................ .............................. 100 W89C841D: 128l lqfp (14 x 20 x 1.4 mm) ................................ ................................ ......................... 101
w 89c841f /d - 4 - 1. general descripti on w89c841f is a highly integrated pci fast ethernet mac controller with embedded ethernet transceiver for 100basetx, 100basefx and 10baset. it is compliant with ieee 802.3, 802.3u specification. auto cross - over function is suppo rted on tp terminal and the network status of w89c841f is indicated by 3 led pins. w89c841f supports full/half duplex, asymmetrical flow control operation compliant with ieee 802.3x and vlan tagged frame compliant with ieee 802.1p. according to different applications, w89c841f can be configured into one of 3 modes to operate by setting the pins config[1:0] and modesel[2:0] after power - on reset. the 3 operational modes of w89c841f are listed as below. 1. pci ethernet mac controller with internal ethernet ph yceiver. 2. pure pci ethernet mac controller 3. pure 10/100m phyceiver w89c841f provides a host bus interface complying with the pci local bus specification r2.2, mini pci specification r1.0 and cardbus. w89c841f plays as a bus master role to improve netw ork performance and reduce the bus utilization. there are built - in 2k bytes tx fifo and 2k bytes rx fifo to store data. the dma controller handles the data transfer between the host memory and the fifos. the data received from network are queued into the r x fifo then directly moved into the host memory through the pci bus. on the other hand, the transmitted data are fetched from the host memory and directly queued into the transmit fifo. no extra on - board memory is needed for data buffering during operation . for pc99/2001, w89c841f implements power management function that are compliant with advanced configuration and power interface (acpi) specification r1.0, pci power management interface specification r1.1 and network device class power management referen ce specification v1.0a. w89c841f supports d3 cold power management state if auxiliary power is detected. 3 types of wakeup events are acceptable like link status change, magic packet and 5 sets of wake - up frames. eeprom (93c46) is supported by w89c841f to s tore configuration and vital product data (vpd) information. the length of vpd information is up to 64 bytes. w89c841f can access the cardbus information structure (cis) information that is stored at eeprom (93c56) or bootrom. w89c841f also supports bootro m/flash interface to read/write bootrom or flash memory. 2. features integrated fast ethernet mac controller with10/100m ethernet transceiver in one chip supports mii interface for programmable single phyceiver or single mac controller complies with ieee 802.3, 802.3u specification supports 10bast - t, 100base - tx and 100base - fx supports auto cross - over operation supports half duplex and full duplex for 10/100m operation supports flow control for full duplex mode compliant with ieee 802.3x
w89c841f /d pub lication release date: october 1 8 , 2001 - 5 - revision a3 co mplies with ieee802.3ac, 802.1q for vlan - tagged frame supports led pins for network activity indication configurable to pci, minipci or cardbus bus interface supports pci/minipci bus master mode for dma operation, fully compliant with pci local bus specification r2.2 and mini pci specification r1.0 supports cardbus information structure (cis) supports 25 to 33 mhz pci clock speed compliant with apci r1.0, pci power management r1.1 and network device class power management reference specificat ion v1.0a supports power management event asserted from d3 (cold) device state with auxiliary power existing supports wakeup function for link status change, magic packet and 5 sets of wakeup frames supports vital product data (vpd) data structure up to 64 bytes s upports 2 sets of independent embedded 2k bytes fifo for transmit and receive flexible multicast address filtering modes - 64 - bit hash - table - all multicast and promiscuous supports 25 mhz crystal or oscillator as internal clock source provides eeprom (93c46 or 93c56) to store configuration parameters, vpd, and cis information supports 8kb to 256 kb bootrom interface for both prom and flash memory 3.3v powered i/os with 5v tolerant inputs packaged in 128 - pin pqfp for w89c841f / l qfp for W89C841D
w 89c841f /d - 6 - 3. pin configuration s vcc btadd11 btadd10 btadd9 btadd8 btadd7 btadd6 btadd5 btadd4 btadd3 btadd2 btadd1 btadd0 gnd vcc_core ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 gnd vcc c_beb0 btdata4/disfefi btdata3/selfx btdata2/eedo btdata1/eedi btdata0/eeck eecs vcc gnd pwgd stk_rstb clkrunb wol/cstschg intab pci_rstb pciclk gnd vcc_core gntb reqb pmeb ad31 ad30 ad29 ad28 ad27 vcc 103 105 110 115 120 125 128 64 60 55 50 45 40 btdata5/ modesel [0] btdata6/ modesel [1] btdata7/ modesel [2] btcsb btoeb/auxpwr btweb/eesel osc/x1 x2 gnda vcca2 control vref rtx gnda vcc3a vcca2 tp/fxin tp/fxip gnda tp/fxon tp/fxop gnd vcc_core led_lnkact led_spd leddupcol config1 config0 scan_en btadd17 btadd16 gnd vcc_core btadd15 btadd14 btadd13 btadd12 gnd 102 100 95 90 85 80 75 70 65 w89c841f (integrated) 1 5 10 15 20 25 30 35 38 gnd ad26 ad25 ad24 c_beb3 idsel ad23 ad22 ad21 vcc gnd ad20 ad19 ad18 ad17 ad16 c_beb2 frameb irdyb vcc gnd trdyb devselb stopb perrb serrb par c_beb1 ad15 vcc gnd ad14 ad13 ad12 ad11 ad10 ad9 ad8 figure 1. w89c841f pin configuration (integrated)
w89c841f /d pub lication release date: october 1 8 , 2001 - 7 - revision a3 pin configurations, continued vcc rxer txer txclk txen txd0 txd1 txd2 txd3 col crs mdio mdc gnd vcc_core ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 gnd vcc c_beb0 nc nc eedo eedi eeck eecs vcc gnd pwgd stk_rstb clkrunb wol/cstschg intab pci_rstb pciclk gnd vcc_core gntb reqb pmeb ad31 ad30 ad29 ad28 ad27 vcc 103 105 110 115 120 125 128 64 60 55 50 45 40 modesel [0] modesel [1] modesel [2] nc auxpwr eesel nc nc gnda vcca2 control nc nc gnda vcc3a vcca2 nc nc gnda nc nc gnd vcc_core link speed duplex config1 config0 scan_en rxd3 rxd2 gnd vcc_core rxd1 rxd0 rxdv rxclk gnd 102 100 95 90 85 80 75 70 65 w89c841f (mac controller) 1 5 10 15 20 25 30 35 38 gnd ad26 ad25 ad24 c_beb3 idsel ad23 ad22 ad21 vcc gnd ad20 ad19 ad18 ad17 ad16 c_beb2 frameb irdyb vcc gnd trdyb devselb stopb perrb serrb par c_beb1 ad15 vcc gnd ad14 ad13 ad12 ad11 ad10 ad9 ad8 figure 1. w89c841f pin configuration (mac c ontroller)
w 89c841f /d - 8 - pin configurations, continued vcc rxer txer txclk txen txd0 txd1 txd2 txd3 col crs mdio mdc gnd vcc_core recful rec100 recan xoven paurec phya0 phya1 phya2 gnd vcc nc disfefi selfx nc nc nc nc vcc gnd pwgd stk_rstb nc nc nc phy_rstb pciclk gnd vcc_core gntb nc nc nc nc nc nc nc vcc 103 105 110 115 120 125 128 64 60 55 50 45 40 modesel [0] modesel [1] modesel [2] nc auxpwr eesel osc/x1 x2 gnda vcca2 control vref rtx gnda vcc3a vcca2 tp/fxin tp/fxip gnda tp/fxon tp/fxop gnd vcc_core led_lnkact led_spd led_dupcol config1 config0 scan_en rxd3 rxd2 gnd vcc_core rxd1 rxd0 rxdv rxclk gnd 102 100 95 90 85 80 75 70 65 w89c841f ( phyceiver ) 1 5 10 15 20 25 30 35 38 gnd nc nc nc nc idsel nc nc nc vcc gnd nc nc nc nc nc nc nc nc vcc gnd nc nc nc nc cn nc nc nc vcc gnd nc nc nc pwrdn int phya4 phya3 figure 1. w89c841f pin configuration (phyceiver)
w89c841f /d pub lication release date: october 1 8 , 2001 - 9 - revision a3 4. pin description pci interface signal name pin typ. pin no. description pciclk i 117 pci clock input a. normal and mac mode w89c841f supports pci clock rate ran ged from 25 mhz to 33 mhz continuously. all pci signals except pci_rstb and intab are referenced on the rising edge of this clock. b. phyceiver mode this pin should be pulled low. pci_rstb/ phy_rstb i 116 pci hardware reset signal (normal and mac mode) wh en asserted (active low), all pci output pins of w89c841f will be in high impedance state, and all open drain signals will be floated. the configurations inside w89c841f will be in its initial state. this signal must be asserted for a period of at least 10 pci clocks to correctly take effect of a reset on hardware. phyceiver reset (phyceiver mode) this pin is used as to reset phyceiver. ad[31:12] io/ts 123 - 127, 2 - 4, 7 - 9, 12 - 16, 29, 32 - 34 pci multiplexed address[31:12] and data bus[31:12] during t he first cycle that frameb asserts, they act as an address bus; on the other cycles, they are switched to be a data bus. ad[11]/ pwrdn io/ts/ i 35 pci multiplexed address[11] and data bus[11] (normal and mac mode) power down enable (phyceiver mode) 1: pow er saving. 0: normal. ad[10]/ int io/ts/ o 36 pci multiplexed address[10] and data bus[10] (normal and mac mode) phy interrupt (phyceiver mode) output low that is asserted to indicate an active interrupt event has occurred.
w 89c841f /d - 10 - pci interface, continued sig nal name pin typ. pin no. description ad[9:5]/ phya[4:0] io/ts/ i 37 - 38, 42 - 44 pci multiplexed address[9:5] and data bus[9:5] (normal and mac mode) phy address (phyceiver mode) these pins indicate phyceiver?s address used for mii magement function ad[4]/ paurec io/ts/ i 45 pci multiplexed address[4] and data bus[4] (normal and mac mode) pause capability recommend (phyceiver mode) this pin is recommended value for capability at full duplex operation. 1: with pause capability 0: no pause capability ad[3]/ xoven io/ts/ i 46 pci multiplexed address[3] and data bus[3] (normal and mac mode) auto cross over enable (phyceiver mode) in twist pair mode, this pin controls the function of cross over. 1: enable 0: disable ad[2]/ recan io/ts/ i 47 pci multipl exed address[2] and data bus[2] (normal and mac mode) auto negotiation enable (phyceiver mode) 1: enable 0: disable ad[1]/ rec100 io/ts/ i 48 pci multiplexed address[1] and data bus[1] (normal and mac mode) recommend 100m (phyceiver mode) 1: 100m 0: 10m ad[0]/ recful io/ts/ i 49 pci multiplexed address[1] and data bus[1] (normal and mac mode) recommend duplex (phyceiver mode) 1: full duplex 0: half duplex
w89c841f /d pub lication release date: october 1 8 , 2001 - 11 - revision a3 pci interface, continued signal name pin typ. pin no. description c_beb[3:0] io/ts 5, 17, 28, 39 multiplexed command and byte enables these signals are driven by current bus master. during address phase, they mean a bus command. on the other phase, they present the byte enable of the transaction. par io/ts 27 parity signal this par represents the ev en parity across ad[31:0] and c_beb[3:0]. it has the same timing as ad[31:0] but is delayed by one clock. frameb io/sts 18 pci cycle frame the current bus master asserts frameb to indicate the beginning and duration of a bus access. this signal keeps asse rted while the current transaction is ongoing and keeps deasserted to indicate that the next data phase is the final data phase. irdyb io/sts 19 initiator ready the irdyb is asserted by the current initiator to indicate the ability to complete the data tr ansfer at the current data phase. the initiator asserts irdyb to indicate the valid write data, or to indicate it is ready to accept the read data. more than or exactly one wait state will be inserted if irdyb is deasserted during the current transaction. data is transferred at the clock rising edge when both irdyb and trdyb are asserted at the same time. trdyb io/sts 22 target ready asserted by the current target to indicate ability to complete data transfer at the current data phase. when w89c841f is o perating at the bus slave mode, it asserts trdyb to indicate that the valid read data presents on the bus or to indicate it is ready to accept data. wait states will be inserted if trdyb is deasserted. data is transferred at the rising edge of the pci cloc k when irdyb and trdyb are both asserted at the same time. stopb io/sts 24 pci stop asserted by the current target to request pci bus master to stop the current transaction.
w 89c841f /d - 12 - pci interface, continued signal name pin typ. pin no. description idsel i 6 pc i initialization device select a. normal and mac mode asserted by host to signal the configuration access request to w89c841f. b. phyceiver mode this pin should be pulled to low. devselb io/sts 23 pci device select asserted by the current target to indica te that it has finished decoding its address as the current access target. when w89c841f is the current master, it checks if the target asserted this signal within 5 pci clocks after having issued command. if not, w89c841f will abort the access operation, releases pci bus access right and acts no more bus master. when w89c841f is the target, it asserts devselb in a medium speed, i.e., within 2 clocks. reqb o/ts 121 pci request asserted by w89c841f to request bus ownership. reqb will be tri - stated when rstb asserted. gntb i/ts 120 pci grant a. normal and mac mode asserted by host to grant that w89c841f have got the bus ownership. when rstb asserted, w89c841f will ignore gntb. b. phyceiver mode this pin should be pulled to high. perrb io/sts 25 pci parity e rror asserted by the current data receiptor. when w89c841f acts the bus master, if a data parity error is detected and the parity error response bit (f04/fcs[6]) is also set, it will set both bits of f04/fcs[24] and c14/cisr[13] as 1 to terminate the curre nt transaction after the current data phase is finished. when w89c841f acts the target, if a data parity error is detected and the bit f04/fcs[6] is set, it will assert perrb only.
w89c841f /d pub lication release date: october 1 8 , 2001 - 13 - revision a3 pci interface, continued signal name pin typ. pin no. description serrb o/od 26 system error this pin is asserted with one pci clock width within two pci clocks after an address parity error is detected, and keeps in high impedance state when idle. the interrupt function caused by this event is gated by the bits in f04/fcs reg ister. w89c841f will assert serrb and will set a high to the detect parity error bit f04/fcs[31] and the signal system erro bit f04/fcs[30] if an address parity error is detected and serrb enable bit f04/fcs[8] is previously set to 1. the bus error status bit c14/cisr[13] will be set to high if both an address parity error is detected and the parity error response bit f04/fcs[6] is set to high. intab o/od 115 interrupt a intab is asserted when any one of unmasked interrupt bits in c14/cisr is set. it keeps asserted until all of the unmasked interrupt bits is cleared.
w 89c841f /d - 14 - power management interface signal name pin typ. pin no. description stk_rstb i/pu 112 sticky reset signal a. normal and mac mode sticky_resetb is a hardware reset signal which is generated from auxiliary power circuit if motherboard supports auxiliary power. so w89c841f can generate pmeb from d3 (cold) state to d0 state transition and preserve pme context bits: pme_status and pme_enable. b. phyceiver mode this pin should be floating. pwgd i 111 power good a. normal and mac mode when pwgd = 1, w89c841f is put in normal operation mode. when pwgd = 0, it isolates any pci input and has all pci outputs kept in high impedance state. the pci bus power can be off by operating system. b. phyceiver mo de this pin should be pulled to high. pmeb o/od 122 power management event the pmeb signal indicates that a power management event has occurred, i.e. there is a magic packet received in suspend mode of host. clkrunb i/od 113 clock run clkrunb is used to request starting or speeding up the pci clock. it also indicates the pci clock status. w89c841f requests the central resource to start, speed up, or maintain the pciclk by the assertion of clkrunb. for the central resource, clkrunb is an s/t/s signal. the central resource is responsible for maintaining clkrunb asserted and for driving it high to deasserted state.
w89c841f /d pub lication release date: october 1 8 , 2001 - 15 - revision a3 power management interface, continued signal name pin typ. pin no. description wol/ cstschg o 114 wake on lan signal the wol signal indicates t hat a wake up event (magic packet, link status change and wake - up frame) has been received. it is used to inform motherboard to execute wake - up process. the motherboard must support wake - on - lan. there are 4 types of output: active high (default), active lo w, positive pulse, negative pulse. cstschg signal: this signal is used in cardbus application only and is used to inform motherboard to execute wake - up process whenever there is pmeb occurs. it is always an active high signal. bootrom/flash and eeprom i nterface signal name pin typ. pin no. pin description btadd[17:14]/ rxd[3:0]_mac/ rxd[3:0]_phy i/o/ i/ o 73, 72, 69, 68 bootrom address (normal mode) these pins are used as rom address pins. mii receive data (mac mode) these pins are used to input mii rxd signals. mii receive data (phyceiver mode) these pins are used to output mii rxd signals. btadd[13]/ rxdv_mac/ rxdv_phy i/o/ i/ o 67 bootrom address (normal mode) this pin is used as rom address pin. mii receive data valid (mac mode) this pin is used to input mii rxdv signal. mii receive data valid (phyceiver mode) this pin is used to output mii rxdv signal. btadd[12]/ rxclk_mac/ rxclk_phy i/o/ i/ o 66 bootrom address (normal mode) these pins are used as rom address pin. mii receive clock (mac mode) th is pin is used to input mii rxclk signal. mii receive clock (phyceiver mode) this pin is used to output mii rxclk signal.
w 89c841f /d - 16 - bootrom/flash and eeprom interface, continued signal name pin typ. pin no. pin description btadd[11]/ rxer_mac/ rxer_phy i/o/ i/ o 63 bootrom address (normal mode) these pins are used as rom address pin. mii receive error (mac mode) this pin is used to input mii rxer signal. mii receive error (phyceiver mode) this pin is used to output mii rxer signal. btadd[10]/ txer_mac/ txer_phy i/o/ o/ i 62 bootrom address (normal mode) these pins are used as rom address pin. mii transmit error (mac mode) this pin is used to output mii txer signal. mii transmit error (phyceiver mode) this pin is used to input mii txer signal. btadd[9]/ txclk_m ac/ txclk_phy i/o/ i/ o 61 bootrom address (normal mode) these pins are used as rom address pin. mii transmit clock (mac mode) this pin is used to input mii txclk signal. mii transmit error (phyceiver mode) this pin is used to output mii txclk signal. bt add[8]/ txen_mac/ txen_phy i/o/ o/ i 60 bootrom address (normal mode) these pins are used as rom address pin. mii transmit enable (mac mode) this pin is used to output mii txen signal. mii transmit enable (phyceiver mode) this pin is used to input mii txe n signal. btadd[7:4]/ txd[3:0]_mac/ txd[3:0]_phy i/o/ o/ i 59, 58, 57, 56 bootrom address (normal mode) these pins are used as rom address pins. mii transmit data (mac mode) these pins are used to output mii txd signals. mii transmit data (phyceiver mode) these pins are used to input mii txd signals.
w89c841f /d pub lication release date: october 1 8 , 2001 - 17 - revision a3 bootrom/flash and eeprom interface, continued signal name pin typ. pin no. pin description btadd[3]/ col_mac/ col_phy i/o/ i/ o 55 bootrom address (normal mode) this pin is used as rom address pin. mii col lision (mac mode) this pin is used to input mii col signal. mii collision (phyceiver mode) this pin is used to output mii col signal. btadd[2]/ crs_mac/ crs_phy i/o/ i/ o 54 bootrom address (normal mode) this pin is used as rom address pin. mii carrier s ense (mac mode) this pin is used to input mii crs signal. mii carrier sense (phyceiver mode) this pin is used to output mii crs signal. btadd[1]/ mdio_mac/ mdio_phy i/o 53 bootrom address (normal mode) this pin is used as rom address pin. mii managemen t data (mac mode) this pin is used to input/output mii mdio signal. mii management data (phyceiver mode) this pin is used to input/output mii mdio signal. btadd[0]/ mdc_mac/ mdc_phy i/o/ o/ i 52 bootrom address (normal mode) these pins are used as rom ad dress pin. mii management clock (mac mode) this pin is used to output mii mdc signal. mii management clock (phyceiver mode) this pin is used to input mii mdc signal. btdata[7:5]/ modesel[2:0] i/o 100 - 102 bootrom data[7:5] these pins are used as rom data pins. mode selection when power - on, these pins are used as input pins to latch the setting value of modesel. mode config modesel normal 00 000 mac controller 01 011 phyceiver 10 000 testing 11 xxx
w 89c841f /d - 18 - bootrom/flash and eeprom interface, continued signal name pin typ. pin no. pin description btdata[4] i/o 103 bootrom data[4] a. normal mode this pin is used as rom data pin. b. phyceiver mode and mac mode this pin should be pulled to low. btdata[3]/ sel fx i/o/ i 104 bootrom data[3] this pin is used as rom data pin fx/tx selection when power - on, this pin is used as input pin to latch the setting value of selfx. 1: fx mode 0: tx mode btdata[2]/ eedo/ phy_duplex i/o/ o 105 bootrom data[2]/ eeprom data ou tput (normal mode and mac mode) this is pin is used for bootrom data pin or eeprom data output dependent on the bit eesel of register dc4/deear. phy_duplex (phyceiver mode) this pin output the phyceiver duplex status. 1: half duplex 0: full duplex btdata[ 1]/ eedi i/o 106 bootrom data[1]/ eeprom data input this is pin is used for bootrom data signal or eeprom data input dependent on the bit eesel of register dc4/deear. btdata[0]/ eeck i/o 107 bootrom data[0]/ eeprom data clock this is pin is used for bootr om data signal or eeprom data clock dependent on the bit eesel of register dc4/deear. eecs o 108 eeprom chip select btcsb o 99 bootrom chip select
w89c841f /d pub lication release date: october 1 8 , 2001 - 19 - revision a3 bootrom/flash and eeprom interface, continued signal name pin typ. pin no. pin description btoeb/ auxpwr i/o 98 bootrom read enable/ auxiliary power detection a. normal mode and mac mode after power on latch, auxiliary power is automatically detected by w89c841f. if auxiliary power is detected to be high, wake - up event generation from d3(cold) to d0 (uninit ialized) state is supported. b. phyceiver mode this pin should be pulled to low. btweb/ eesel i/o 97 bootrom write enable/ eeprom type select a. normal mode and mac mode after power on latch, eeprom type is detected by w89c841f. if it is high, eeprom (93c 56) is used for cardbus application. otherwise, eeprom (93c46) is used in pci/mini pci application. b. phyceiver mode this pin should be pulled to low. transceiver interface signal name pin typ. pin no. pin description tp/fxop o 82 twist pair / fiber tr ansmit output positive tp/fxon o 83 twist pair / fiber transmit output negative tp/fxip i 85 twist pair / fiber receive input positive tp/fxin i 86 twist pair / fiber receive input negative osc/x1 i 96 25 mhz crystal/osc clock input x2 o 95 crystal ou tput left unconnected when oscillator is chosen for x1 input. vref i 91 rc input for bias. rtx i 90 rc input for transmitter. control o 92 2.5v regulator control output drive current below 10 ma.
w 89c841f /d - 20 - led interface signal name pin typ. pin no. pin descript ion led_ lnkact i/o 79 led_lnkact 0: link up without activity. 1: link fail or activity is on (flash 100 ms) led_spd i/o 78 led_spd 0: 100m. 1: 10m. led_ dupcol i/o 77 led_dupcol 0: full duplex or collision in half duplex (flash 100 ms) 1: half duplex a nd no collision. configuration and test interface signal name pin typ. pin no. pin description config[1:0] i 76, 75 configuration 00: normal mode 01: mac controller mode (disable internal phyceiver and disable boot rom function) 10: phyceiver mode (disab le mac controller and boot rom function) 11: reserved for testing scan_en i 74 scan enable reserved for testing. this pin should be pulled to low. power pins signal name pin typ. pin no. pin description v cc a2 87, 93 2.5v analog power v cc 3a 88 3.3v a nalog power gnda 84, 89, 94 analog ground v cc 10, 20, 30, 40, 64, 109, 128 3.3v i/o digital power v cc _core 50, 70, 80, 119 2.5v core digital power gnd 1, 11, 21, 31, 41, 51, 65, 71, 81, 110, 118 digital ground
w89c841f /d pub lication release date: october 1 8 , 2001 - 21 - revision a3 pins mapping table w89c841f can be co nfigured into 3 different operational types. in the following table, it lists the pin mapping of different configuration mode. normal mode mac controller mode phyceiver mode config = 00 modesel [2:0] = 000 config = 01 modesel [2:0] = 011 config = 10 modes el [2:0] = 000 led_lnkact link (i) led_lnkact (o) led_spd speed (i) led_spd (o) led_dupcol duplex (i) led_dupcol (o) btadd17 rxd3 (i) rxd3 (o) btadd16 rxd2 (i) rxd2 (o) btadd15 rdx1 (i) rdx1 (o) btadd14 rdx0 (i) rdx0 (o) btadd13 rxdv (i) rxdv (o) btadd12 rxclk (i) rxclk (o) btadd11 rxer (i) rxer (o) btadd10 txer (o) txer (o) btadd9 txclk (i) txclk (o) btadd8 txen (o) txen (i) btadd7 txd0 (o) txd0 (i) btadd6 txd1 (o) txd1 (i) btadd5 txd2 (o) txd2 (i) btadd4 txd3 (o) txd3 (i) btadd3 col (i) col (o) btadd2 crs (i) crs (o) btadd1 mdio (i/o) mdio (i/o) btadd0 mdc (o) mdc (i) btdata7 modesel[2] modesel[2] btdata6 modesel[1] modesel[1] btdata5 modesel[0] modesel[0] btdata4 nc nc
w 89c841f /d - 22 - pins mapping table, continued normal mode mac controller m ode phyceiver mode config = 00 modesel [2:0] = 000 config = 01 modesel [2:0] = 011 config = 10 modesel [2:0] = 000 btdata3 nc selfx btdata2/ eedo eedo phy_dpulex btdata1/ eedi eedi nc btdata0/ eeclk eeclk nc btcsb nc nc btoeb nc nc btweb nc nc ad1 1 ad11 pwrdn (i) ad10 ad10 int (o) ad9 ad9 phya[4] (i) ad8 ad8 phya[3] (i) ad7 ad7 phya[2] (i) ad6 ad6 phya[1] (i) ad5 ad5 phya[0] (i) ad4 ad4 paurec (i) ad3 ad3 xoven (i) ad2 ad2 recan (i) ad1 ad1 rec100 (i) ad0 ad0 recful (i)
w89c841f /d pub lication release date: october 1 8 , 2001 - 23 - revision a3 5. block diagr am pci tx fifo rx fifo media access controller mii data buffer long word aligning buffer pci bus master pci bus slave controller configuration registers status registers control registers transmit data dma machine receive data dma machine mii control signals eeprom access interface expansion rom interface memory interface pci interface data driver xcvr media figure 2. w89c841f block diagram
w 89c841f /d - 24 - 6. system diagram nic product: pci lan card, card bus lan card, minipci lan card figure 3. nic application home networking pr oduct: homepna figure 4. homepna application lan on mother board: lom figure 5. lom application rj45 w89c841f 25 mhz eeprom led boot rom/flash magnetic p c i i/f w89c841f mac home pna mii phy w89c841f chipset mac mii
w89c841f /d pub lication release date: october 1 8 , 2001 - 25 - revision a3 pci application: restore card, firewall, education system figure 6. restore card application 7. functional descr iption operation mode configuration w89c841f can be configured to 3 different operation modes for different applications. in the following table, the assignment of pins config[1:0] and modesel[2:0] is listed. pin assignment normal mac controller phyceiver config[1:0] 00 01 10 mode_sel[2:0] 000 011 000 in the normal mode, w89c841f is used in the nic application. in the mac controller mode, w89c841f that is used as a mac controller plus homephy that is used as a transceiver implement a homepna card. in t he phyceiver mode, an application like lan on motherboard (lom) is implemented by w89c841f that is used as a single phyceiver plus pc chipset. phyceiver an internal phyceiver is embedded in w89c841f. it is compatible with ieee802.3 10 - bast - t, 100base - tx an d 100bast - fx. w89c841f can be configured to twist pair interface or fiber interface. auto - negotiation and auto - crossover function is supported. w89c841f provides 3 leds to indicate link/activity, speed and duplex/collision status. direct memory access func tion on receiving a data packet, the receive dma function will transfer these data from the internal receive fifo which has a size of 2k bytes to the host memory with the assistance of the on - chip pci bus master. during the transaction cycle, the media acc ess controller (mac) requests the receive dma state machine to move the data in the receive fifo onto the pci bus, and then move it to the host memory. eeprom w89c841f flash (application s/w) pci i/f
w 89c841f /d - 26 - w89c840f transmit dma function performs the data transfer from the host memory through on - chip pci bus master into the internal 2 kbytes transmit fifo. the transmit dma state machine will request the mac to send out the data in the tx fifo onto the transmission media. media access control (mac) function the mac function of w89c841f fully meets the requirem ents defined by the ieee802.3u specification. mac performs many transmission functions, including the inter - frame spacing function, collision detection, collision enforcement, collision backoff and retransmission. mac performs the receive functions includi ng the address recognition function, the frame check sequence validation, the frame disassembly, framing and collision filtering. full duplex and half duplex function in the half duplex mode, the mac should perform the transmission or reception operation at the different time frame. simultaneous transmission and reception is not allowed. however, in the time duration from 10 bits time to 16 bits time after the packet is transmitted, the active col signal is recognized as a sqe test signal but not a collisi on event. the active signal crs will be recognized as a loopback carrier sense signal when the mac is transmitting a packet. the carrier sense lost status is relied on the crs. normally, there should not be any carrier sense lost during transmitting if the media and devices are functional. in the full duplex mode, the mac can perform the transmission and receive operation at the same time. collision event, sqe lost and carrier sense lost are not defined in the full duplex mode. after auto - negotiation comple ted, network duplex mode can be decided by internal phyceiver. network media speed function w89c841f can work at network speed of 100m or 10mbps. after auto - negotiation completed, network speed can be decided by internal phyceiver. flow control in full d uplex mode w89c841f supports asymmetrical and symmetrical flow control in full duplex mode compliant with ieee802.3x. after auto - negotiation completed, w89c841f will decide to operate in which flow control mode (symmetrical, asymmetrical or none). when th e receiving byte counts of rx fifo is over the high threshold defined at field htv of register ddc/drfctv[17:9], a pause frame with max pause time (ffffh) is transmitted to prevent the other station keeping on transmitting packets to w89c841f. so w89c841f will not drop packets due to rx fifo overflow. when the receiving byte count of rx fifo is below the low threshold defined at field ltv of register ddc/drfctv[8:0], a pause frame with min pause time (0000h) is transmitted to let the other station starting to transmit packets to w89c841f. if w89c841f receives a pause packet with non - zero pause time, the packet transmission ability will be inhibited until the pause time counts down to 0. pause frame is a flow control packet. it is not a data packet and will b e dropped by w89c841f. priority tagged frame supporting qos a priority tagged frame defined at ieee 802.1p contains a vlan tag which indicates the user priority and null vlan id (vid = 0). w89c841f can transmit and receive priority tagged frames to improv e the network quality of service if bit vlanen of register c1c/cncr is set.
w89c841f /d pub lication release date: october 1 8 , 2001 - 27 - revision a3 eeprom auto - load and software programming function w89c841f reads configuration parameter from eeprom and stores these data into the configuration registers and function register s after hardware reset. eeprom 93c46 or 93c56 will be the choice as the storage device for storing these data according to different application. in pci/mini - pci application, w89c841f stores configuration parameters and vital product data (vpd) in eeprom 9 3c46. configuration parameters and relative register are listed below: 1) 6 bytes ethernet address (register dcc[31:0] and dd0[15:0]) 2) 1 byte maximum latency (register f3c[31:24]) 3) 1 byte minimum grant (register f3c[23:16]) 4) 2 bytes subsystem id (registe r f2c[31:16]) 5) 2 bytes subsystem vendor id ( register f2c [15:0] ) 6) 2 bytes device id (register f00[31:16]) 7) 2 bytes vendor id (register f00[15:0]) 8) 4 bytes cardbus cis pointer (register f28[31:0]) 9) 1 bit power management data enable 10) 3 bits auxiliary cu rrent (register fdc[24:22]) 11) 2 bits data scale (register fe0[14:13]) 12) 6 bytes power consumption and dissipation data for d0, d1 and d3 state (register fe0[31:24]) 13) 1 bits power management enable (register d00[6]) 14) 1 bit vpd enable (register d00[5]) 15) 2 bits bus type (register d00[1:0]) 16) 1 bit clkrun enable (register d00[11]) 17) 1 bit magic packet enable (register d00[10]) 18) 3 bits boot rom size (register dc0[30:28]) 19) 1 byte base class code (register f08[31:24]) 20) 1 byte subclass code (register f08[23:16 ]) 21) 1 byte interface code (register f08[15:8] 22) 1 bytes revision id (register f08[7:0] 23) 64 bytes vpd data
w 89c841f /d - 28 - eeprom 93c46 address high byte (bit 15 - bit 8) low byte (bit 7 - bit 0) 00h ethernet address 1 [15:8] ethernet address 0 [7:0] 01h ethernet addr ess 3 [31:24] ethernet address 2 [23:16] 02h ethernet address 5 [47:40] ethernet address 4 [39:32] 03h maxlat mingnt 04h subsystem id (high byte) subsystem id (low byte) 05h subsystem vendor id (high byte) subsystem vendor id (low byte) 06h device id (high byte) device id (low byte) 07h vendor id (high byte) vendor id (low byte) 0 8 h cardbus cis pointer (low word) 0 9 h cardbus cis pointer (high word) 0ah pm_data_en {bit15} reserved 0bh aux_current {bit15 - bit13} data_scale {bit7 - bit6} 0ch d0 pow er consumption data d0 power dissipation data 0dh d1 power consumption data d1 power dissipation data 0eh d3 power consumption data d3 power dissipation data 0fh pm_en {bit15} vpd_en {bit14} pcbustype {bit13 - bit12} ckrun_en {bit11} magp_en {bit10} boo t rom size {bit7 - bit5} 10h base class code subclass code 11h interface code revision id 12 - 1fh reserved reserved 20h - 3fh vital product data (vpd) in cardbus application, another data structure of cardbus information structure (cis) needs to b e stored in the eeprom 93c56. totally 128 bytes space addressed from 40h to 7fh are reserved for cis use.
w89c841f /d pub lication release date: october 1 8 , 2001 - 29 - revision a3 eeprom 93c56 address high byte (bit 15 - bit 8) low byte (bit 7 - bit 0) 00h ethernet address 1 [15:8] ethernet address 0 [7:0] 01h ethernet addre ss 3 [31:24] ethernet address 2 [23:16] 02h ethernet address 5 [47:40] ethernet address 4 [39:32] 03h maxlat mingnt 04h subsystem id (high byte) subsystem id (low byte) 05h subsystem vendor id (high byte) subsystem vendor id (low byte) 06h device id ( high byte) device id (low byte) 07h vendor id (high byte) vendor id (low byte) 08h cardbus cis pointer (low word) 09h cardbus cis pointer (high word) 0ah pm_data_en {bit15} reserved 0bh aux_current {bit15 - bit13} data_scale {bit7 - bit6} 0ch d0 power consumption data d0 power dissipation data 0dh d1 power consumption data d1 power dissipation data 0eh d3 power consumption data d3 power dissipation data 0fh pm_en {bit15} vpd_en {bit14} pcbustype {bit13 - bit12} clkrun_en {bit11} magp_en {bit10} boot rom size {bit7 - bit5} 10h base class code subclass code 11h interface code revision id 12h - 1fh reserved reserved 20h - 3fh vital product data (vpd) 40h - 7fh cardbus information structure
w 89c841f /d - 30 - dc4/deear register is used as an interface to access the data between the system and eeprom. the following table lists the reading and writing steps for eeprom. command step eeprom read set eeprom access bit eesel to 1. set eeprom offset address to bits eeoa set eeprom read command to bit eerw set start eepro m read/write command to bit starteerw waiting for read operation completed until bit starteerw change to 0. read data from bits eedata. disable eeprom write protection set eeprom access bit eesel to 1. set eeprom write protection disable command to bit eerw set start eeprom read/write command to bit starteerw waiting for write protection disable operation completed until bit starteerw change to 0. eeprom write 1) set eeprom access bit eesel to 1. 2) set eeprom offset address to bits eeoa 3) set eeprom d ata to bits eedata 4) set eeprom write command to bit eerw 5) set start eeprom read/write command to bit starteerw 6) waiting for write operation completed until bit starteerw change to 0. enable eeprom write protection set eeprom access bit eesel to 1. set eeprom write protection enable command to bit eerw set star eeprom read/write command to bit starteerw. waiting for bit starteerw change to 0. bootrom read and flash programming function w89c841f can address up to 256 kbytes memory space for the on - b oard bootrom or flash memory device. the on - board bootrom device will be mapped into the host memory by the system bios. w89c841f will return the mapped memory address depending on the field bootrom size select of register dc0/dbrar[30:28]. this field is l oaded from eeprom after power on reset. the relationship between the return value from the register f30/ferba and the field bootrom size select of register dc0/dbrar[30:28] is listed as the following table.
w89c841f /d pub lication release date: october 1 8 , 2001 - 31 - revision a3 rom size dc0/dbrar[30:28] f30/ferba none 000b 0000_0000h none 001b 0000_0000h 8 kbytes 010b ffff_e001h 16kbytes 011b ffff_c001h 32kbytes 100b ffff_8001h 64kbytes 101b ffff_0001h 128kbytes 110b fffe_0001h 256kbytes 111b fffc_0001h the address decoder of w89c841f for accessing the on - boar d bootrom will be enabled if both the bit 0 of f30/ferba and the bit 1 of f04/fcs are set to high at the same time. on - board boot rom data will be fetched by w89c841f and are loaded into the host memory. on the other hand, the address decoder will be disab led if the bit 0 of f30/ferba is reset to 0. under this case, w89c841f will ignore the dc0/dbrar, no matter what content it has. usually on - board bootrom data can be read by the system bios during host system booting or power - on reset. w89c841f also prov ides an access method by register dc0/dbrar and dc0/deear[31] to read or write flash memory on restore card applications. if bootrom interface is chosen to be accessed, the bit eesel of register dc4/deear[31] must be set to 0 at first. the read and write p rocess for bootrom or flash through register dc0/dbrar is listed in the following table. command step read 1) set bootrom access bit eesel (dc4/deear[31]) to 0. 2) set the bootrom/flash offset address to bits broma 3) set bootrom/flash read control bit bromrd to 1. 4) waiting for read operation completed until bit bromrd change to 0. 5) read back the data from bits bromd write 1) set bootrom access bit eesel (dc4/deear[31]) to 0. 2) set the boot rom offset address to bits broma 3) write data to bits bromd 4) set bootrom write cont rol bit bromwr to 1. 5) waiting for write operation completed until bit bromwr change to 0.
w 89c841f /d - 32 - the bit bromrd (bit 27) and bit bromwr (bit 26) of the register dc0/dbrar should not be set to 1 at the same time. in the case of both of the bit bromrd and bit bromwr are 1, it will not properly initialize the read or the write operation for rom device. the application program can check the contents of the register dc0/dbrar to know if the read or write operation is already completed or not. w89c841f will start the read or the write operation when the bit bromrd or bit bromwr are set to high and will be reset automatically after the read/write operation is completed. for the write operation, the software driver should not start up the next write data request unti l the bit bromwr of dc0/dbrar[26] is reset to 0 by w89c841f. for the read operation, the read data will be valid only if the bit bromrd of the register dc0/dbrar[27] is reset to 0 by w89c841f. mii management function w89c841f supports mii management functi on through register dc8/dmmar to access the mii management registers of the internal phyceiver (normal mode) or external phyceiver (mac controller mode). the following table lists the read and write access steps for mii management registers. command step read set phy address to bits phyadd to default value 01h. set phy register address to bits regadd set mdio read command to bit mdiorw set start mdio read/write command to bit startmdiorw waiting for read operation completed until bit startmdiorw change t o 0. read data from bits phydata. write set phy address to bits phyadd to default value 01h set phy register address to bits regadd set phy data to bits phydata set mdio write command to bit mdiorw set start mdio read/write command to bit startmdiorw 6) w aiting for write operation completed until bit startmdiorw change to 0. system resource configuring w89c841f will require the i/o space, memory space for function cxx and dxx registers and the interrupt line to perform the communication between the netwo rk and the host. in pci/minipci system, cxx and dxx registers can be mapped to either system i/o space or memory space. the following table lists the relative mapping address in double word aligned. i/o space address memory space address cxx registers 0 0h - 3ch 000h - 03ch dxx registers 00h - ffh 100h - 1fch
w89c841f /d pub lication release date: october 1 8 , 2001 - 33 - revision a3 in cardbus system, cxx and dxx registers can be mapped to either system i/o space or memory space. but cis data can be mapped to memory space only. the following table lists the relative mapping a ddress in double word. i/o space address memory space address cxx register 00h - 3ch 000h - 03ch cis data x 080h - 0fch dxx register 00h - ffh 100h - 1fch w89c841f uses only one interrupt pin intab. however, the interrupt line resource assignment is determined by the system bios by writing the related data into the bits iline of register f3c/fir[7:0]. power management function w89c841f supports power management function that is compliant with acpi r1.0, pci power management r1.1 and network device cl ass power management reference specification v1.0a. power management state from d0, d1, d3(hot) is provided by w89c841f. but whether the d3(cold) power management state is provided is dependent on the auxiliary power detected or not after power on reset. p ower management d2 is not supported by w89c841f. pme context consists of the bit pme_en of register fe0/fpmr1[8] and bit pme_sts of register fe0/fpmr1[15]. if d3(cold) power management state is supported, pme context will be kept valid. when pmeb is asser ted, it must continue to drive the signal low until software explicitly either clears the pme status bit or clears the pme enable bit. wake - on - lan function if the power management function is enabled, 3 types of wake - up events can be accepted by w89c841f to acknowledge driver that wake - up event has happened. these wake - up events are defined as: link status changed magic packet wake - up frame 8. configuration reg isters the general attributes of the pci configuration registers implemented in w89c841f are described as the following. 1) writes to the reserved configuration registers are treated as no - op. the bus access will complete without affecting any data in w89c841f internal registers. 2) read from the reserved or un - implemented registers will be returned 0 value. 3) softreset has no effect on the pci configuration registers. 4) hardreset will clear the pci configuration registers. 5) the implemented configuration registers support any byte enable combination access.
w 89c841f /d - 34 - 6) burst access to the configur ation registers will be terminated after 1st data transfer completed with a disconnect without data. the following table outlined all the pci configuration registers inside this chip and summarized its function. configuration register mapping code abbrevia tion meaning system i/o offset f00 fid identification 00h f04 fcs command and status 04h f08 frev revision 08h f0c flt latency timer 0ch f10 fbioac base i/o address for cxx registers 10h f14 fbioad base i/o address for dxx registers 14h f18 fbma bas e memory address 18h ---- ----- reserved 1ch - 24h f28 fcispr cardbus cis pointer 28h f2c fssid subsystem id 2ch f30 ferba expansion rom base address 30h f34 fcapr capabilities pointer 34h ---- ----- reserved 38h f3c fir interrupt 3ch f40 fsr sign ature 40h fdc fpmr0 power management register 0 dch fe0 fpmr1 power management register 1 e0h fe4 fvpdr0 vital product data register 0 e4h fe8 fvpdr1 vital product data register 1 e8h
w89c841f /d pub lication release date: october 1 8 , 2001 - 35 - revision a3 this table lists the initial state of each register in w89c841f a fter stk_resetb, pci_resetb, d3tod0_resetb and software reset. code abbr. stk_resetb, pci_rese tb d3tod0_resetb software reset f00 fid 0000_0000h non affected f04 fcs 0280_0000h non affected f08 frev 0200_0000h non affected f0c flt 0000_0000h non affect ed f10 fbioac ffff_ffc1h non affected f14 fbioad ffff_ff01h non affected f18 fbma ffff_fe00h non affected f28 fcispr 0000_0000h non affected f2c fssid 0000_0000h non affected f30 ferba 0000_0000h non affected f34 fcapr 0000_0000h non affected f3c f ir 0000_0100h non affected f40 fsr 0000_0044h non affected fdc fpmr0 5a02_0001h non affected fe0 fpmr1 0000_0100h non affected fe4 fvpdr0 0000_0003h non affected fe8 fvpdr1 0000_0000h non affected f00/fid device id register the register specifies the vendor id and the device id. bit attribute bit name description 31:16 r did device id loaded from eeprom after hardware reset. 15:0 r vid vendor id loaded from eeprom after hardware reset. ffffh is an invalid value for vendor id.
w 89c841f /d - 36 - f04/fcs command and status register the f04/fcs comprises two parts, one is the command register (fcs[15:0]) which provides the control of pci activity, and another is the status register (fcs[31:16]) which shows the status information of pci event. writing 1 to the bits of the status register will clear them; writing 0 has no effect. bit attribute bit name description 31 r/wc dpe detected parity error the dpe bit will be set if a parity error is detected by w89c841f even the parity error response bit of register f04/fcs[6] is disabled. 30 r/wc sse signaled system error the sse bit will be set if w89c841f assert serrb. 29 r/wc rma received master abort the rma bit will be set if w89c841f master transaction is terminated by a master abort. 28 r/wc rta received target abo rt the rta bit will be set if w89c841f master transaction is terminated by a target abort. 27 r/wc sta signaled target abort the sta bit will be set if w89c841f slave transaction takes a target abort. 26:25 r dt devselb timing fixed at 01b. indicate a medium devsel# assert timing. 24 r/wc mdpe master data parity error the mdpe bit will be set if the following three conditions are met: 1). w89c841f asserts perrb (on a read) or observes perrb asserted (on a write). 2). w89c841f acts as a master in the tr ansaction that the error occurs. 3). the parity error response bit of register f04/fcs[6] is set.
w89c841f /d pub lication release date: october 1 8 , 2001 - 37 - revision a3 f04/fcs command and status register, continued bit attribute bit name description 23 r fbtbc fast back - to - back capable fixed at 1. indicates the capability of accepting fast back to back transactions which are not accessing to the same target. 22:21 r --- reserved. fixed at 0. 20 r caps capabilities list the value is d ependent on the pmen and vpden loaded from eeprom to decide the w89c841f power management and vital product data capability. while caps is equal to 1: indicates that w89c841f supports the pci power management and/or vpd. 0: indicates that w89c841f does not support power management and vpd. 19:9 r --- reserved. fixed at 0. 8 r/w se serrb enab le set se bit high to enable w89c841f to assert serrb if an address parity error is detected. this bit and bit per must be set 1 to signal serr event. 7 r ---- reserved. fixed at 0. 6 r/w per parity error response set per bit to high to enable the w89c8 41f to respond to parity error. when per is reset, w89c841f will ignore any parity error and continue the normal operation. w89c841f internal parity checking and generation function will not be disabled even per is reset. 5:3 r --- reserved. fixed at 0. 2 r/w bm bus master set bm bit to high will allow w89c841f acting as a bus master. reset bm bit to low will disable the w89c841f bus master ability. 1 r/w ms memory space set ms bit to high will allow w89c841f to respond to memory space access by the host . 0 r/w ios i/o space set ios bit to high will allow w89c841f to respond to i/o space access by the host.
w 89c841f /d - 38 - f08/frev device revision register this register which is read - only shows class code, subclass code, interface code and revision id. bit attribute b it name description 31:24 r bc base class code loaded from eeprom. 23:16 r sc subclass code loaded from eeprom. 15:8 r ic interface code loaded from eeprom. 7:0 r rev revision id loaded from eeprom. f0c/flt latency timer register this register specifi es the latency timer of master bus in units of pci bus clock. bit attribute bit name description 31:24 r --- reserved, fixed to 0. 23:16 r ht header type, fixed to 0. 15:8 r/w lt latency timer specify, in units of pci clocks, the latency timer value of w89c841f. when w89c841f asserts frameb, its latency timer starts counting up. w89c841f will initiate the transaction termination as soon as its gntb de - asserted if the timer expired before w89c841f de - asserts frameb. 7:0 r --- reserved. fixed at 0. f10/ fbioac base i/o address for cxx function registers this register is written by software after power - on reset to specify w89c841f base i/o address for cxx function registers access in the system. bit attribute bit name description 31: 6 r/w bioa base i/o a ddress written by power - on software to specify base i/o address for cxx function registers. w89c841f requires a 64 bytes i/o space. 5:1 r --- reserved. fixed at 0. 0 r io i/o space indicator fixed at 1.
w89c841f /d pub lication release date: october 1 8 , 2001 - 39 - revision a3 f14/fbioad base i/o address for dxx function regi sters this register is written by software after power - on reset to specify w89c841f base i/o address for dxx function registers in the system. bit attribute bit name description 31: 8 r/w bioa base i/o address written by power - on software to specify base i/o address for dxx function registers. w89c841f requires a 256 bytes i/o space. 7:1 r --- reserved. fixed at 0. 0 r io i/o space indicator fixed at 1. f18/fbma base memory address register this register is written by power - on software to specify w89c84 1f base memory address in the system. bit attribute bit name description 31: 9 r/w bma base memory address written by power - on software to specify base memory address for both of cxx and dxx function registers. w89c841f requires a 512 bytes memory space. 8:1 r --- reserved. fixed at 0. 0 r mem memory space indicator fixed at 0.
w 89c841f /d - 40 - f28/fcispr cardbus cis pointer register this register identifies the location of the card information structure (cis). in w89c841f, cis data can be store d in eeprom or bootrom. cis pointer value is loaded from eeprom. bit attribute bit name description 31:28 r rin rom image number this field defines the rom image number (0 - fh) in which the cis is located. the offset value is added to the start of the rom image to identify the s tart of the cis. 27:3 r aso address space offset this field defines which space the cis resides within. memory space: this is the offset into the memory address space governed by base address register f18/fmba. adding this value to the value in the base a ddress register gives the location of the start address of the cis. bits aso is fixed to 80h. expansion rom space: the offset value is from the start of the rom image identified by bits rin. 2:0 r asi address space indicator specifies the base address wi thin the space indicated. the offset bits aso is added to this base address to identify the start of the cis. the address indicators values are: 3 = cis is in the memory pointed to by the base address register 2. 7 = cis is in the boot rom. bits rin identi fy which boot rom image. other values are reserved. f2c/fssid subsystem id register this register stores the subsystem id and subsystem vendor id. bit attribute bit name description 31:16 r sbid subsystem id loaded from eeprom. 15:0 r sbvid subsystem ve ndor id loaded from eeprom.
w89c841f /d pub lication release date: october 1 8 , 2001 - 41 - revision a3 f30/ferba expansion rom base address register this register is written by power - on software to specify the on - board boot rom base address in the system. bit attribute bit name description 31:13 r/w eromb expansion rom base a ddress written by power - on software to specify expansion rom base address. w89c841f will request up to 256k bytes memory space for the on board boot rom according the configuration of bit bromsel of register dc0/dbrar[30:28]. 12:1 r --- reserved. fixed at 0. 0 r/w rome expansion rom enable set both of this bit and memory space bit of register f04/fcs[1] to 1 to enable expansion rom access ability. f34/fcappr capabilities pointer register w89c841f has the capabilities of power management and/or vital pro duct data. this register is read - only and is used as the start pointer of capabilities list. bit attribute bit name description 31:8 r --- reserved. fixed at 0. 7:0 r cappr capabilities pointer the value is d ependent on the pmen and vpden loaded from ee prom to decide the w89c841f power management and vpd capability. if pmen = 1, cappr is set to dch. if pmen = 0 and vpden = 1, cappr is set to e4h. if pmen = 0 and vpden = 0, cappr is set to 00h.
w 89c841f /d - 42 - f3c/fir interrupt register this register stores the max l atency timer and min grant timer. they are loaded from eeprom. bit attribute bit name description 31:24 r maxlat max latency timer loaded from eeprom. indicates how often, in units of 0.25 m s, w89c841f needs to gain access to pci bus. assuming pci clock rate is 33 mhz. 23:16 r mingnt min grant timer loaded from eeprom. indicates how long a burst period, in units of 0.25 m s, is needed by w89c841f. assuming pci clock rate is 33 mhz. 15:8 r ipin interrupt pin fixed at 01h. indicates intab is used. 7:0 r/w iline interrupt line written by power - on software to specify routing of interrupt line. f40/fsr signature register the register is designed for identifying the hardware of w89c841f. bit attribute bit name description 31:16 r/w dvar driver area this f ield is for driver special use. the driver can write some specific pattern to these bits for bundling the software and hardware of w89c841f together. 15:8 r --- reserved. fixed at 0. 7:0 r sig signature after the hardware reset, these 8 bits value is tog gled as following sig = 70h at (2n - 1)th read 44h at 2nth read where n = 1, 2, ....
w89c841f /d pub lication release date: october 1 8 , 2001 - 43 - revision a3 fdc/fpmr0 power management register 0 the register provides the power management capabilities of w89c841f. bit attribute bit name description 31: 27 r pme_sp pme_suppor t bit 31 = 1 --- pmeb can be asserted from d3(cold) state. the value is dependent on the auxiliary power source detection from pin btoeb/auxpwr after power - on reset. bit 30 = 1 --- pmeb can be asserted from d3 (hot). fixed to 1. bit 29 = 0 --- pmeb cannot be asserted from d2. fixed to 0. bit 28 = 1 --- pmeb can be asserted from d1. fixed to 1. bit 27 = 1 --- pmeb can be asserted from d0. fixed to 1. 26 r d2sup d2_support fixed to 0. w89c841f does not support d2 power management state. 25 r d1sup d1_suppor t fixed to 1. w89c841f supports d1 power management state. 24:22 r aux_ current 3.3v auxiliary current this field reports the 3.3vaux auxiliary current requirements for pci function. if pm_data_en is disable and d3 cold is not supported, aux_current are f ixed to 000b. if pm_data_en is disable and d3 cold is supported, aux_current bits apply: bit 3.3vaux 24 23 22 max. current required 1 1 1 375 ma 1 1 0 320 ma 1 0 1 270 ma 1 0 0 220 ma 0 1 1 160 ma 0 1 0 100 ma 0 0 1 55 ma 0 0 0 0 (self powered) if bit pm_data_en loaded from eeprom is enabled, pm_data field of fe0/fpmr1 is implemented to report the power consumption and power dissipation of each device state (d0, d1 and d3). so it takes precedence over 3.3vaux current requirement reporting. aux_current bits will be fixed to 000b. note: the 3.3vaux max. auxiliary current of w89c841f is 220 ma which should be loaded from eeprom. r --- fixed to 0.
w 89c841f /d - 44 - fdc/fpmr0 power management register 0, continued bit attribute bit name description 18:16 r vers version fixed at 010b. the w89c841f complies with revision 1.1 of the pci power management interface specification 15:8 r nxtpr next item pointer the value is d ependent on the vpden loaded from eeprom to decide the w89c841f vpd capability link list pointer. if vpden = 1, nxtpr is equal to e4h. if vpden = 0, nxtpr is equal to 00h. 7:0 r cap_id capability identifier fixed to 01h. this linked list item is the pci power manage ment registers. fe0/fpmr1 power management register 1 the register provides the power management control, status and power consumption, dissipation data of supported device power states. bit attribute bit name description 31:24 r pm_data pm_data if bit pm_data_en loaded from eeprom is enabled, pm_data is u sed to report the state dependent data requested by the d_select field. the value is scaled by the value reported by the d_scale field. all of the pm_data will be loaded from eeprom after power on reset . 23:16 r --- reserved. fixed at 0. 15 sticky bit, r/wc pme_sts pme status this bit is set when the enabled wake - up frame detector receives a wake - up frame or the enabled magic packet detector receives a magic packet or the enabled link status change det ector detected a link status change independent of the state of the pme_en bit. when pme_sts and pme_en are set, w89c841f asserts pmeb. writing a 1 to this bit will clear it and cause w89c841f to stop asserting a pmeb (if pme_en is enable). writing a 0 has no effect. this bit defaults to 0 if pmeb generation from d3cold is not supported if pmeb generation from d3cold is supported, then this bit is sticky and must be explicitly cleared by the operating system each time it is initially loaded.
w89c841f /d pub lication release date: october 1 8 , 2001 - 45 - revision a3 fe0/fpmr1 pow er management register 1, continued bit attribute bit name description 14:13 r d_scale data scale indicates the scaling factor to be used when interpreting the value of the pm_data field. the value is loaded from eeprom. 00b = unknown 01b = 0.1x 10b = 0.0 1x 11b = 0.001x 12:9 r/w d_select data select used to select which data is to be reported in units watts through the pm_data and d_scale fields. 0 = d0 power consumed 1 = d1 power consumed 3 = d3 power consumed 4 = d0 power dissipated 5 = d1 power dissipa ted 7 = d3 power dissipated others = reserved note: the power consumption and power dissipation of w89c841f at different power state are: 1. d0: 0.59w 2. d1: 0.59w 3. d3: 0.52w 8 sticky bit, r/w pme_en pme enable when set to 1, pmeb assertion is enable d. when reset to 0, pmeb assertion is disabled. when pme_sts and pme_en are set, w89c841f asserts pmeb. this bit defaults to 0 if pmeb generation from d3cold is not supported. if pmeb generation from d3cold is supported, then this bit is sticky and must be explicitly cleared by the operating system each time it is initially loaded. 7:2 r --- reserved. fixed at 0. 1:0 r/w pw_sts power state 00b --- indicates w89c841f at d0 power state 01b --- indicates w89c841f at d1 power state 11b --- indicates w89c841f at d3 (hot) power state writing 10b has no effect.
w 89c841f /d - 46 - fe4/fvpdr0 vital product data register 0 the register provides control and status capability for the data transfer between register fe8/fvpdr1 and eeprom. bit attribute bit name description 31 r/w vpdfl ag vpd flag a flag used to indicate when the transfer of data between the vpd data register (fvpdr1) and eeprom is completed. a. read vpd information 1. reset vpdflag to 0, and write vpd address to vpdaddr. 2. vpdflag will be set to 1, after 4 bytes data are read from eeprom to register fvpdr1 b. write vpd information 1. write the data to register fvpdr1. 2. set vpdflag to 1, and write vpd address to vpdaddr. 3. vpdflag will be reset to 0, after 4 bytes data are written from register fvpdr1 to eeprom. 30:16 r/w vpdaddr vpd ad dress it is used to access vpd data that is stored in eeprom. the lower 2 bits of vpdaddr must be zero. 15:8 r nextid pointer to next id fixed at 00h. there is no next item pointer in the capabilities list. 7:0 r vpdid vpd id fixed at 03h. it indicates c apability structure id for vpd fe8/fvpdr1 vital product data register 1 the register provides the buffer for vpd from system or eeprom. bit attribute bit name description 31:0 r/w vpd_data vpd data vpd data are read or written through this register. the least significant byte of this register corresponds to the byte of vpd at the address specified by the bits vpdaddr of register fe4/fvpdr0.
w89c841f /d pub lication release date: october 1 8 , 2001 - 47 - revision a3 9. function register s w89c841f implements two types of function registers: cxx and dxx. cxx function registers are used to perform the function control and status monitor of w89c841f. dxx function registers are used to control power management parameters, monitor power management status and setup wake - up frames parameters. the general attributes of w89c841f function r egisters are described as the following : 1) the function registers of w89c841f can be mapped into the host i/o space or memory space. 2) the registers of the w89c841f are double word aligned. each register consists of 32 bits and may be accessed using any byte - e nable combinations with double word aligned address. 3) burst access to the registers of w89c841f will be terminated after 1st data transfer completed with a disconnect without data. 4) softreset will have the same effect as done by hardreset on the registers of w89c841f, except for the function registers c34/cma0, c38/cma1, d00/dwupc - d6c/dbwf4bm3, dcc/dpa0, dd0/dpa1 and df0/dfer - dfc/dffer and configuration registers 5) any read on the reserved register will be returned with 0 value. cxx function registers the f ollowing table outlined all the control/status registers in w89c841f, offset address, and summarized its function. code abbr. meaning base offset from fbioac base offset from fbma c00 cbcr bus control 00h 000h c04 ctsdr transmit start demand 04h 004h c0 8 crsdr receive start demand 08h 008h c0c crdla receive descriptor list address 0ch 00ch c10 ctdla transmit descriptor list address 10h 010h c14 cisr interrupt status 14h 014h c18 cimr interrupt mask 18h 018h c1c cncr network configuration 1ch 01ch c20 cfdcr frame discarded counter 20h 020h c24 ctdar current transmit descriptor address 24h 024h c28 ctbar current transmit buffer address 28h 028h c2c crdar current receive descriptor address 2ch 02ch c30 crbar current receive buffer address 30h 030h c34 cma0 multicast address 0 34h 034h c38 cma1 multicast address 1 38h 038h c3c cgtr general timer register 3ch 03ch
w 89c841f /d - 48 - this table lists the initial state of each register in w89c841f after stk_resetb, pci_resetb, d3tod0_resetb and software reset. code a bbr. stk_resetb, pci_rese tb d3tod0_resetb software reset c00 cbcr 0001_0010h 0001_0010h c04 ctsdr 0000_0000h 0000_0000h c08 crsdr 0000_0000h 0000_0000h c0c crdla 0000_0000h 0000_0000h c10 ctdla 0000_0000h 0000_0000h c14 cisr 0000_0000h 0000_0000h c1 8 cimr 0000_0000h 0000_0000h c1c cncr 0000_0130h 0000_0130h c20 cfdcr 0000_0000h 0000_0000h c24 ctdar 0000_0000h 0000_0000h c28 ctbar 0000_0000h 0000_0000h c2c crdar 0000_0000h 0000_0000h c30 crbar 0000_0000h 0000_0000h c34 cma0 0000_0000h not affec ted c38 cma1 0000_0000h not affected c3c cgtr 0000_0000h 0000_0000h the detail function and operation for each register in w89c841f will be described in the following paragraph. c00/cbcr pci bus control register this register defines the configuration of pci bus master. bit attribute bit name description 31:22 r ---- reserved. fixed to 0. 21 r/w wait wait state insertion when wait is set, w89c841f as a bus master executes memory read/write with one wait state every data phase. when wait is reset, w89 c841f as a bus master executes memory read/write with zero wait state every data phase. 20 r/w dbe descriptor big endian mode when set, the descriptors will be handled in big endian mode. when reset, the descriptors will be treated in little endian mode
w89c841f /d pub lication release date: october 1 8 , 2001 - 49 - revision a3 c00/cbcr pci bus control register, continued bit attribute bit name description 19:17 r --- reserved. fixed at 0. 16 r/w pae pci abort enable 1: if bus error happened, txdma and rxdma will halt. driver must reinitialized w89c841f. (default) 0: if bus e rror happened, txdma and rxdma will not halt. wrong data will not be written into register of configuration space, cxx or dxx. 15:14 r/w ca cache alignment ca defines the address boundary for the burst access to the data transmission or reception. when th e starting address of the data burst access is not aligned, more specifically, the starting address should be a multiple of some number such as 4, 8 etc. w89c841f will have the first burst transfer that causes that the next burst access will has the start address aligned. after the first burst occurred, all other burst operation are aligned with the configuration of ca accordingly. the ca must be initialized with a non - zero value after reset. the alignment configuration is as following: [00] reserve d (default) [01] 8 double word alignment [10] 16 double word alignment [11] 32 double word alignment 13:8 r/w bl burst length bl defines the maximum number of the double words that can be transferred within one pci burst transactio n. the burst length configuration is as following. 00h refer to ca 01h 1 double word 02h 2 double word 04h 4 double word 08h 8 double word 10h 16 double word 20h 32 double word other reser ved
w 89c841f /d - 50 - c00/cbcr pci bus control register, continued bit attribute bit name description 7 r/w bbe buffer with big endian when set, the data buffers are treated with big endian ordering. when reset, the data buffers are treated with little endian ordering. 6:2 r/w skip skip length between descriptors this field specifies the skip length between two descriptors from the start address of the current descriptor to the start address of the next descriptor. the unit of the skip length is double word. the default value after hardware reset is 04h. 1 r/w arb arbitration between tx and rx processes when reset, the tx process and rx process will have the right to use the internal bus with the same priority. when set, the rx process will have higher priority than tx process with regarding to the internal bus utilization. 0 r/w swr software reset. set bit sw_reset to high will reset most internal registers except registers c34/cma0, c38/cma1, d00/dwupc - d6c /dbwf4bm3, dcc/cpa0, dd0/cpa1, df0/dfer - dfc /dffer and pc i configuration registers. c04/ctsdr transmit start demand register this register is used to request w89c841f to do a transmission process. bit attribute bit name description 31:0 w tsd transmit start demand a write to this register will trigger w89c841 f transmit dma to fetch the descriptor for progressing the transmission operation when w89c841f transmit dma is staying at the suspend state. otherwise, the write operation will have no effect.
w89c841f /d pub lication release date: october 1 8 , 2001 - 51 - revision a3 c08/crsdr receive start demand register the register is us ed to request w89c841f to do a receive process. bit attribute bit name description 31:0 w rsd receive start demand a write to this register will trigger w89c841f receive dma to fetch the descriptor for progressing the receiving operation when w89c841f rec eive dma is staying at the suspend state. otherwise, the write operation will have no effect. c0c/crdla receive descriptors list addresses the register defines the start address of the receive descriptor list. it should be updated only when the receive d ma state machine is staying at the stop state. bit attribute bit name description 31:2 r/w srl start address of receive list 1:0 r/w mbz must be written as 0 for double word alignment. c10/ctdla transmit descriptors list addresses the register defines t he start address of the transmit descriptor list. it should be updated only when the transmission dma state machine is staying at the stop state. bit attribute bit name description 31:2 r/w stl start address of transmit list 1:0 r/w mbz must be written a s 0 for double word alignment. c14/cisr interrupt status register most bits of this register report the interrupt status. the assertion of the interrupt status, reported by bits 0 to bit 14 and the corresponding interrupt mask bits will cause a hardware i nterrupt to the host. a write with 1 value the status bit will clear them and write 0 will have no effect.
w 89c841f /d - 52 - c14/cisr interrupt status register, continued bit attribute bit name description 31:26 r --- reserved. fixed at 0. 25:23 r bet bus error type the field indicates the error type of bus error and is valid only when bit 13, bus error, is set. assertion of these bits does not generate interrupt. the definition of bus error is as follows. 000 = parity error (master mode) 001 = master abort (ma ster mode) 010 = target abort (master mode) 011 = signaled system error (slave mode) 100 = data parity error (slave mode) 101 - 111 = reserved the initial state of this field after reset is 0. 22:20 r tps transmit process state this field indicates the transmit state. this field does not generate interrupt. 19:17 r rps receive process state this field indicates the receive state. this field does not generate interrupt. 16 r nir normal interrupt report the normal interrupt report includes transmit completed interrupt, transmit buffer unavailable interrupt, the receive completed interrupt and the receive pause packet interrupt. the nir is a logical or result of the bits 0, 2, 6, 14 of register c14/cisr. only the bits corresponding to the unm asked bits of c18/cimr will affect this bit. 15 r air abnormal interrupt report the abnormal interrupt includes transmit process in idle state interrupt, receive early interrupt, receive error interrupt, transmit fifo under - flow interrupt, receive buffer unavailable interrupt, receive in idle state interrupt, eeprom programming fail interrupt , transmit early interrupt, timer expire interrupt, phy interrupt and the bus error interrupt. the air is a logical or result of the bits 1, 3, 4, 5, 7, 8, 9, 10, 11, 12, 13 of register c14/cisr. only these bits corresponding to the unmasked bits of the c18/cimr will affect this bit.
w89c841f /d pub lication release date: october 1 8 , 2001 - 53 - revision a3 c14/cisr interrupt status register, continued bit attribute bit name description 14 r/wc rpp receive pause packet interrupt a high ind icates a pause packet is received. 13 r/wc be bus error interrupt a high indicates a bus error happened. the error type will be shown by bit 25 - 23. 12 r pi phy interrupt a high indicates a phy interrupt happened. phy interrupt event is stored in globa l interrupt status register [address 14h] of mii management. after reading global interrupt status register, that register and this bit will be cleared. 11 r/wc te timer expired interrupt a high indicates the general timer of register c3c/cgtr expired. 1 0 r/wc tei transmit early interrupt w89c841f will has transmit early interrupt status set after the packet to be transmitted is completely transferred into the transmit fifo if transmit early interrupt on bit of c1c/cncr[30] is set. the tei will be cleared automatically after the packet is transmitted out from the transmit fifo completely. 9 r/wc epf eeprom programming fail interrupt a high indicates a programming error happened when w89c841f tries to write data into eeprom that is in write protected state . 8 r/wc ridle receive in idle state set means the receive dma state machine is in the idle state. 7 r/wc rbu receive buffer unavailable when there is no receive buffer available, this bit is set and the receive process enters the suspend state. 6 r/w c rint receive complete interrupt a high indicates that a frame has been received and the receive status is transferred into the receive descriptors of the current frame. 5 r/wc tuf transmit fifo under - flow a high indicates that the transmit fifo had an u nder - flow error during the packet transmission.
w 89c841f /d - 54 - c14/cisr interrupt status register, continued bit attribute bit name description 4 r/wc rerr receive error a high indicates that the receive dma detects a receive error during the packet reception. 3 r/ wc rei receive early interrupt the rei will be set when the number of the data of the incoming frame, in double word unit, transferred to the data buffer reaches receive early interrupt threshold specified by the register c1c/cncr[28:21] if receive early i nterrupt on in the register c1c/cncr[31] is set. 2 r/wc tbu transmit buffer unavailable a high indicates that there is no available transmit descriptor during or after the packet transmission. 1 r/wc tidle transmit process in idle state a high indicate s the transmit state machine is in the idle state. 0 r/wc tint t ransmit complete interrupt the tini will be set when a frame transmission is completed and the fint (bit 31) of transmit descriptor 1 (t01) is set. c18/cimr interrupt mask register the regis ter controls the interrupt enable corresponding to the bits in the register c14/cisr bit attribute bit name description 31:17 r ---- reserved. fixed to 0. 16 r/w nie normal interrupt enable the normal interrupt will be enabled if the nie is set to high. the normal interrupt is disabled when the nie is reset to low. the hardware interrupt will be asserted if both the nie bit of the c18/cimr[16] and the nir bit of the c14/cisr[16] are set to high. 15 r/w aie abnormal interrupt enable the abnormal interrup t will be enabled if the aie is set to high. the abnormal interrupt is disabled when the aie is reset to low. the hardware interrupt will be asserted if both the aie bit of the c18/cimr[15] and the air bit of the c14/cisr[15] are set to high.
w89c841f /d pub lication release date: october 1 8 , 2001 - 55 - revision a3 c 18/cimr in terrupt mask register, continued bit attribute bit name description 14 r/w rppe receive pause packet interrupt enable the receive pause packet interrupt will be enabled if both aie and bppe are set to high, otherwise, the receive pause packet interrupt wi ll be disabled. 13 r/w bee bus error enable the bus error interrupt will be enabled if both aie and bee are set to high, otherwise, the bus error interrupt will be disabled. 12 r/w pie phy interrupt enable. the phy interrupt will be enabled if both aie and pie are set to high, otherwise, the phy interrupt will be disabled. 11 r/w tee timer expired enable the timer expired interrupt will be enabled if both aie and tee are set to high, otherwise, the timer expired interrupt will be disabled. 10 r/w teie transmit early interrupt enable the transmit early interrupt will be enabled if both aie and teie are set to high, otherwise, the transmit early interrupt will be disabled. 9 r/w epfe eeprom programming fail enable: the eeprom programming fail will be ena bled if both aie and epfe are set to high, otherwise, the eeprom programming fail will be disabled. 8 r/w rie receive idle enable. the receive idle interrupt will be enabled if both aie and rie are set to high, otherwise, the receive idle interrupt will b e disabled. 7 r/w rbue receive buffer unavailable enable. the receive buffer unavailable interrupt will be enabled if both aie and rbue are set to high, otherwise, the receive buffer unavailable interrupt will be disabled. 6 r/w rinte receive complete in terrupt enable the receive interrupt will be enabled if both nie and rinte are set to high, otherwise, the receive interrupt will be disabled. 5 r/w tfue transmit fifo underflow enable the transmit fifo underflow interrupt will be enabled if both aie and tfue are set to high, otherwise, the transmit fifo underflow interrupt will be disabled.
w 89c841f /d - 56 - c 18/cimr interrupt mask register, continued bit attribute bit name description 4 r/w rerre receive error enable the receive error interrupt will be enabled if both aie and rerre are set to high, otherwise, the receive error interrupt will be disabled. 3 r/w reie receive early interrupt enable the receive early interrupt will be enabled if both aie and reie are set to high, otherwise, the receive early interrupt will be disabled. 2 r/w tbue transmit buffer unavailable enable the transmit buffer unavailable interrupt will be enabled if both nie and tbue are set to high, otherwise, the transmit buffer unavailable interrupt will be disabled. 1 r/w tie transmit idle ena ble the transmit idle interrupt will be enabled if both aie and tie are set to high, otherwise, the transmit idle interrupt will be disabled. 0 r/w tinte transmit complete interrupt enable the transmit interrupt will be enabled if both nie and tinte are s et to high, otherwise, the transmit interrupt will be disabled. c1c/cncr network configuration register the register defines the configuration for the data transmission or reception and the interrupt algorithm for interrupt assertion. bit attribute bit na me description 31 r/w reio receive early interrupt on the receive early interrupt function will be enabled when the reio is set to high. otherwise, receive early interrupt function will be disabled. 30 r/w teio transmit early interrupt on the transmit ea rly interrupt function will be enabled when the teio is set to high. otherwise, transmit early interrupt function will be disabled. 29 r es ethernet speed 1: 100 mbps 0: 10 mbps.
w89c841f /d pub lication release date: october 1 8 , 2001 - 57 - revision a3 c1c/cncr network configuration register, continued bit attribute bit name description 28:21 r/w reit receive early interrupt threshold during receiving packet, the w89c841f will assert an interrupt request when the bytes number of the received data, which the receive dma has moved them into the data buffer, excesses receive ear ly interrupt threshold. to set this field 00h will disable receive early interrupt function. the setting of receive early interrupt threshold is as following. 01h 4 bytes 02h 8 bytes -- -- 0fh 60 bytes 10h 64 bytes -- -- ffh 1020 bytes 20:14 r/w tth transmit threshold these bits select the transmit threshold level of the transmit fifo. the packet transmission will be started immediately once the data queued into the transmit fifo has reached the threshold level. the transmission will also be started immediately when the full packet has been transferred into the transmit fifo even though the frame length is less than the tth level. to change this bit, the transmit state machine must be in idle state. the fo llowing table shows there is a difference with 16 bytes for each consecutive setting value in this field, except that the first one in the table. 00h full packet 01h 16 bytes 02h 32 bytes -- -- 0fh 240 bytes 10h 256 bytes -- -- 7fh 2032 bytes 13 r/w txon transmit on when set, the transmission process will be started. when reset, the transmission state machine will be stopped after the current frame is completed
w 89c841f /d - 58 - c1c/cncr network configuration reg ister, continued bit attribute bit name description 12 r /w vlanen vlan enable 1 : w89c841f can transmit and receive packet with vlan tagged whose maximum length is equal to 1 522 bytes . 0: o nly un tagged frame are transmitted and recei ved. packet length up to 1518 bytes is allowed. (default) 11:10 r/w lbk loopback mode the lbk selects the w89c841f loop - back modes: 00 normal mode (default) 01 internal loop - back 10 external loop - back reserved 9 r fd full duplex mode 1: full du plex mode. 0: half duplex mode. 8 r/w adp accept directed packet when set, all incoming packets with a directed address will be accepted. 7 r/w aep accept error packet when set, all incoming crc error packets passed address filtering will be accepted. 6 r/w arp accept runt packet when set, the incoming packets pass the address filtering with the length less than 64 bytes are accepted. 5 r/w abp accept broadcast packet. when set, all incoming packets with a broadcast address will be accepted. 4 r/w amp accept multicast packet when set, all incoming packets with a multicast address match the node multicast address table (mar7 - mar0) will be accepted. 3 r/w app accept all physical packet when set, all incoming packets with unicast address will be a ccepted.
w89c841f /d pub lication release date: october 1 8 , 2001 - 59 - revision a3 c1c/cncr network configuration register, continued bit attribute bit name description 2 r/w rxon receive on. when set, the receive process will be started. when reset, the receive state machine will be stopped after the current frame is comple ted. 1 r/w tfcen tx flow control enable 1: w89c841f can transmit pause packet. 0: w89c841f can not transmit pause packet. (default) 0 r/w rfcen rx flow control enable 1: w89c841f can parse pause packet. 0: w89c841f can not parse pause packet. (default ) c20/cfdcr frame discarded counter register the register records the missed packet count and the fifo overflow count. bit attribute bit name description 31 rc mrfo more receive fifo overflow this bit is the overflow bit of the receive fifo overflow cou nter. the actual number of the fifo overflow must be more than the number shown by the bits rfoc if the mrfo is set to high. this bit will be clear after read. 30:16 rc rfoc receive fifo overflow counter the rfoc indicates the number of the packets that a re discarded due to the receive fifo overflow under the condition of the receive buffer is not available. this counter will be clear after read. 15 rc mmp more missed packets overflow bit of missed packet counter. the actual number of the missed packet mu st be more than the number shown by the bits field mpc if mmp is set tot high. this bit will be clear after read. 14:0 rc mpc missed packet counter the mpc indicates the number of packets that are discarded due to the receive fifo overflow. this counter w ill be clear after read.
w 89c841f /d - 60 - c24/ctdar current transmit descriptor address register the register shows the start address of the descriptor which w89c841f transmit dma state machine is used to process the current frame. bit attribute bit name description 3 1:0 r ctda current transmit descriptor address the ctda represents the start address of the current receive descriptor which w89c841f transmit dma state machine is used to process the transmit frame. c28/ctbar current transmit buffer address register the register shows the address of the system memory from which w89c841f transmit dma state machine will fetch the double word data and queue the data into the fifo for transmission. bit attribute bit name description 31:0 r ctba current receive buffer address the ctba contains the start address of the host memory from which w89c841f transmit dma state machine will fetch the double word data and queue it into the fifo for transmission. c2c/crdar current receive descriptor address register the register shows th e start address of the receive descriptor which is used by w89c841f receive dma state machine to process the current receive frame. bit attribute bit name description 31:0 r crda current receive descriptor address the crda represents the start address of the current receive descriptor which w89c841f receive dma state machine is used to process the received frame. c30/crbar current receive buffer address register the register shows the start address of the host memory which is used by w89c841f receive dma state machine to store the current aligned double word data of the current received frame. bit attribute bit name description 31:0 r crba current receive buffer address the crba contains the pointer current address in the on - using buffer of the host memor y which will be used by w89c841f receive dma state machine to store the current aligned double word data of the current received frame.
w89c841f /d pub lication release date: october 1 8 , 2001 - 61 - revision a3 c34/cma0 multicast address register 0 the register defines the lower 32 bits of the total 64 bits multicast address has hing table. bit attribute bit name description 31:24 r/w mar3 muticast address 3 the mar3 defines the bit 31 - 24 of the hashing table. 23:16 r/w mar2 muticast address 2 the mar2 defines the bit 23 - 16 of the hashing table. 15:8 r/w mar1 muticast addre ss 1 the mar1 defines the bit 15 - 8 of the hashing table. 7:0 r/w mar0 muticast address 0 the mar0 defines the bit 7 - 0 of the hashing table. c38/cma1 multicast address register 1 the register defines the upper 32 bits of the 64 bits multicast address hashing table. bit attribute bit name description 31:24 r/w mar7 muticast address 7 the mar7 defines the bit 63 - 56 of the hashing table. 23:16 r/w mar6 muticast address 6 the mar2 defines the bit 55 - 48 of the hashing table. 15:8 r/w mar5 muticast ad dress 5 the mar1 defines the bit 47 - 40 of the hashing table. 7:0 r/w mar4 muticast address 4 the mar4 defines the bit 39 - 32 of the hashing table. c3c/cgtr general timer register the register shows the real time content of w89c841f internal general ti mer. bit attribute bit name description 31 r/w atlp accept too long packet when set, a packet whose length is longer than 1518 (1522) bytes is received. when reset, a packet whose length is longer than 1518 (1522) bytes is not received. default to 0. 30: 17 r --- reserved. fixed at 0.
w 89c841f /d - 62 - c3c/cgtr general timer register, continued bit attribute bit name description 16 r/w recur recursive mode 1: the value of bits timer in the register c3c/cgtr[15:0] can be reloaded for internal general timer to count down w hen the internal general reaches zero. 0: no recursive to the internal general timer. (default) 15:0 r/w timer general timer the bits timer shows the content of the general timer inside the w89c841f. the internal general timer will count down from the pre - set value, a non zero value, programmed by the driver automatically. the time unit for the internal general timer count_down is approximately 2048 times the cycle duration of the mii txclk. for instance, the count down time unit for a 25 mhz mii txclk is approximately 82 m s. dxx function registers the following table outlined all the dxx function registers for power management control and status, eeprom, boot rom, phy?s registers access and cardbus status/event in w89c841f. code abbr. meaning base offset from fbioad base offset from fbma d00 dwupc wake - up control and status 00h 100h d04 - d08 reserved d0c dwf0crc wake - up frame b0b1 crc 0ch 10ch d10 dwf1crc wake - up frame b2b3 crc 10h 110h d14 dwf2crc wake - up frame b4 crc 14h 114h d18 - d1c reserved d20 dbwf0bm0 basic wake - up frame 0 byte - mask 0 20h 120h d24 dbwf0bm1 basic wake - up frame 0 byte - mask 1 24h 124h d28 dbwf0bm2 basic wake - up frame 0 byte - mask 2 28h 128h d2c dbwf0bm3 basic wake - up frame 0 byte - mask 3 2ch 12ch d30 dbwf1bm0 ba sic wake - up frame 1 byte - mask 0 30h 130h d34 dbwf1bm1 basic wake - up frame 1 byte - mask 1 34h 134h d38 dbwf1bm2 basic wake - up frame 1 byte - mask 2 38h 138h d3c dbwf1bm3 basic wake - up frame 1 byte - mask 3 3ch 13ch
w89c841f /d pub lication release date: october 1 8 , 2001 - 63 - revision a3 dxx function registers, continued code abb r. meaning base offset from fbioad base offset from fbma d40 dbwf2bm0 basic wake - up frame 2 byte - mask 0 40h 140h d 44 dbwf2bm1 basic wake - up frame 2 byte - mask 1 44h 144h d4 8 dbwf2bm2 basic wake - up frame 2 byte - mask 2 48h 148h d4 c dbwf2bm3 basic wake - up frame 2 byte - mask 3 4ch 14ch d50 dbwf3bm0 basic wake - up frame 3 byte - mask 0 50h 150h d54 dbwf3bm1 basic wake - up frame 3 byte - mask 1 54h 154h d58 dbwf3bm2 basic wake - up frame 3 byte - mask 2 58h 158h d5c dbwf3bm3 basic wake - up frame 3 byte - mask 3 5ch 1 5ch d60 dbwf4bm0 basic wake - up frame 4 byte - mask 0 60h 160h d64 dbwf4bm1 basic wake - up frame 4 byte - mask 1 64h 164h d68 dbwf4bm2 basic wake - up frame 4 byte - mask 2 68h 168h d6c dbwf4bm3 basic wake - up frame 4 byte - mask 3 6ch 16ch d70 - dbc --- reserv ed dc0 dbrar boot rom access c0h 1c0h dc4 deear eeprom access c4h 1c4h dc8 dmmar mii management access c8h 1c8h dcc dpa0 physical address 0 cch 1cch dd0 dpa1 physical address 1 d0h 1d0h dd4 --- reserved dd8 --- reserved ddc drfctv rxdma flow control threshold value dch 1dch df0 dfer function event register f0h 1f0h df4 dfemr function event mask register f4h 1f4h df8 dfpsr function present status register f8h 1f8h dfc dffer function force event register fch 1fch
w 89c841f /d - 64 - this table lists the ini tial state of each register in w89c841f after stk_resetb, pci_resetb, d3tod0_resetb and software reset. code abbr. stk_resetb, pci_rese tb, d3tod0_resetb software reset d00 dwupc 0000_0458h non affected d04 - d08 reserved d0c dwf0crc fffe_fffeh non affected d10 dwf1crc fffe_fffeh non affected d14 dwf2crc fffe_0000h non affected d18 - d1c reserved d20 dbwf0bm0 0000_0000h non affected d24 dbwf0bm1 0000_0000h non affected d28 dbwf0bm2 0000_0000h non affected d2c dbwf0bm3 0000_0000h non affec ted d30 dbwf1bm0 0000_0000h non affected d34 dbwf1bm1 0000_0000h non affected d38 dbwf1bm2 0000_0000h non affected d3c dbwf1bm3 0000_0000h non affected d40 dbwf2bm0 0000_0000h non affected d44 dbwf2bm1 0000_0000h non affected d48 dbwf2bm2 0000_0000h non affected d4c dbwf2bm3 0000_0000h non affected d50 dbwf3bm0 0000_0000h non affected d54 dbwf3bm1 0000_0000h non affected d58 dbwf3bm2 0000_0000h non affected d5c dbwf3bm3 0000_0000h non affected d60 dbwf4bm0 0000_0000h non affected d64 dbwf4bm1 0000_0000h non affected d68 dbwf4bm2 0000_0000h non affected d6c dbwf4bm3 0000_0000h non affected d70 - dbc reserved dc0 dbrar 0000_0000h 0000_0000h dc4 deear 0000_0000h 0000_0000h dc8 dmmar 4020_0000h 4020_0000h dcc dpa0 0000_0000h non affecte d
w89c841f /d pub lication release date: october 1 8 , 2001 - 65 - revision a3 continued code abbr. stk_resetb, pci_rese tb, d3tod0_resetb software reset dd0 dpa1 0000_0000h non affected dd4 reserved dd8 reserved ddc drfctv 0003_0100h 0003_0100h df0 dfer 0000_0000h non affected df4 dfemr 0000_0000h non affected df8 dfp sr 0000_0000h non affected dfc dffer 0000_0000h non affected d00/dwupcs wake - up control and status register bit attribute bit name description 31 r/wc rmgp received magic packet when set, indicates that a magic packet has been received if magic packet d etector is enabled. 30 r/wc dlscd_ l2f detected link status change from link to fail when set, indicates that a link status change from link to fail if link status changes from link to fail detector enable (lscde_l2f = 1). 29 r/wc dlscd_ f2l detected l ink status change from fail to link when set, indicates that a link status change from fail to link if link status changes from fail to link detector enable (lscde_f2l = 1). 28:21 r --- reserved. fixed to 0. 20 r/wc rwupf4 received wake - up frame 4 when set, indicates that a wake - up frame 4 has been received if wake - up frame detector is enabled (wupfe= 1). 19 r/wc rwupf3 received wake - up frame 3 when set, indicates that a wake - up frame 3 has been received if wake - up frame detector is enabled (wupfe= 1). 18 r/wc rwupf2 received wake - up frame 2 when set, indicates that a wake - up frame 2 has been received if wake - up frame detector is enabled (wupfe= 1).
w 89c841f /d - 66 - d00/dwupcs wake - up control and status register, continued bit attribute bit name description 17 r/w c rwupf1 received wake - up frame 1 when set, indicates that a wake - up frame 0 has been received if wake - up frame detector is enabled (wupfe = 1). 16 r/wc rwupf0 received wake - up frame 0 when set, indicates that a wake - up frame 0 has been received if wake - up frame detector is enabled (wupfe = 1). 15:14 r --- reserved. fixed at 0. 13 r/w pwrdn phy power down enable if bus type is cardbus which is loaded from eeprom, bit pwrdn is default to high (active) to force phy into power down mode after power on res et. if bus type is not cardbus, bit pwrdn is default to low to disable power down mode after power on reset. 1: phy power down enable 0: phy power down disable 12 r eetype eeprom type after power on reset, eeprom type will be latched in from pin btweb/ees el. 1: 93c56 0: 93c46 11 r/w clkrun_en clockrun enable this bit is loaded from eeprom to control pin clkrunb in minipci or cardbus system. 1: enable clockrun function. 0: disable clockrun function. 10 r/w mgpe magic packet detector enable loaded from eep rom. setting to 1 and pmen bit is true enable the operation of magic packet detector. 9 r/w lscde_l2f link status change from link to fail detector enable setting to 1 and pmen bit is true enable the operation of link status change from link to fail dete ctor.
w89c841f /d pub lication release date: october 1 8 , 2001 - 67 - revision a3 d00/dwupcs wake - up control and status register, continued bit attribute bit name description 8 r/w lscde_f2l link status change from fail to link detector enable setting to 1 and pmen bit is true enable the operation of link status change from fai l to link detector. 7 r/w wupfe wake - up frame detector enable setting to 1 and pmen bit is true enable the operation of wake - up frame detector. 6 r/w pmen power management enable loaded from eeprom. 1: pm enable, => function pmeb and wol function are en abled. 0: pm disable (default) => function pmeb and wol are all disable. bits mgpe, lscde_l2f, lscde_f2l and wupfe are all fixed to 0. 5 r/w vpden vital product data enable loaded from eeprom. 1: vpd data is stored in eeprom. 0: vpd data is not stored in eeprom. (default) 4:3 r/w woltp wake on lan signal type it indicates the signal type of pin wol/cstschg. 00: negative pulse (125ms) 01: positive pulse (125ms) 10: active low 11: active high (default) 2 r auxpwr aux power status this bit is loaded from p in btoeb/auxpwr to indicate auxiliary power status. 1: aux power is on. 0: aux power is off. 1:0 r bustp pc bus type these 2 bits are loaded from eeprom to configure w89c841f pc bus type. 00: pci 01: minipci 10: cardbus 11: reserved.
w 89c841f /d - 68 - d0c/dwbf0crc wake - up frame b0b1 crc register bit attribute bit name description 31:16 r/w wfb0crc crc - 16 value for basic wake - up frame 0 match setting to all 1?s except bit[16], after power - on reset. 15:0 r/w wfb1crc crc - 16 value for basic wake - up frame 1 match setting to a ll 1?s except bit[0], after power - on reset. d10/dwf1crc wake - up frame b2b3 crc register bit attribute bit name description 31:16 r/w wfb2crc crc - 16 value for basic wake - up frame 2 match setting to all 1?s except bit[16], after power - on reset. 15:0 r/w w fb3crc crc - 16 value for basic wake - up frame 3 match setting to all 1?s except bit[0], after power - on reset. d14/dwf2crc wake - up frame b4 crc register bit attribute bit name description 31:16 r/w wfb4crc crc - 16 value for basic wake - up frame 4 match sett ing to all 1?s except bit[16], after power - on reset. 15:0 r wfb3crc reserved. fixed to 0. d20/dbwf0bm0 basic wake - up frame 0 byte - mask 0 register bit attribute bit name description 31:0 r/w wf0bm0 basic wake - up frame 0 byte - mask 0 the bit 0 is the byte 1 mask of basic wake - up frame 0. --- the bit 31 is the byte 32 mask of basic wake - up frame 0. setting to 0, after power - on reset. d24/dbwf0bm1 basic wake - up frame 0 byte - mask 1 register bit attribute bit name description 31:0 r/w wf0bm1 basic wake - up fr ame 0 byte - mask 1 the bit 0 is the byte 33 mask of basic wake - up frame 0. --- the bit 31 is the byte 64 mask of basic wake - up frame 0. setting to 0, after power - on reset.
w89c841f /d pub lication release date: october 1 8 , 2001 - 69 - revision a3 d28/dbwf0bm2 basic wake - up frame 0 byte - mask 2 register bit attribute bit name desc ription 31:0 r/w wf0bm2 basic wake - up frame 0 byte - mask 2 the bit 0 is the byte 65 mask of basic wake - up frame 0. --- the bit 31 is the byte 96 mask of basic wake - up frame 0. setting to 0, after power - on reset. d2c/dbwf0bm3 basic wake - up frame 0 byte - ma sk 3 register bit attribute bit name description 31:0 r/w wf0bm3 basic wake - up frame 0 byte - mask 3 the bit 0 is the byte 97 mask of basic wake - up frame 0. --- the bit 31 is the byte 128 mask of basic wake - up frame 0. setting to 0, after power - on reset. d30/dbwf1bm0 basic wake - up frame 1 byte - mask 0 register bit attribute bit name description 31:0 r/w wf1bm0 basic wake - up frame 1 byte - mask 0 the bit 0 is the byte 1 mask of basic wake - up frame 1. --- the bit 31 is the byte 32 mask of asic wake - up frame 1. setting to 0, after power - on reset. d34/dbwf1bm1 basic wake - up frame 1 byte - mask 1 register bit attribute bit name description 31:0 r/w wf1bm1 basic wake - up frame 1 byte - mask 1 the bit 0 is the byte 33 mask of basic wake - up frame 1. --- the bit 31 is t he byte 64 mask of basic wake - up frame 1. setting to 0, after power - on reset. d38/dbwf1bm2 basic wake - up frame 1 byte - mask 2 register bit attribute bit name description 31:0 r/w wf1bm2 basic wake - up frame 1 byte - mask 2 the bit 0 is the byte 65 mask of b asic wake - up frame 1. --- the bit 31 is the byte 96 mask of basic wake - up frame 1. setting to 0, after power - on reset.
w 89c841f /d - 70 - d3c/dbwf1bm3 basic wake - up frame 1 byte - mask 3 register bit attribute bit name description 31:0 r/w wf1bm3 basic wake - up frame 1 byte - mask 3 the bit 0 is the byte 97 mask of basic wake - up frame 1. --- the bit 31 is the byte 128 mask of basic wake - up frame 1. setting to 0, after power - on reset. d40/dbwf2bm0 basic wake - up frame 2 byte - mask 0 register bit attribute bit name description 3 1:0 r/w wf2bm0 basic wake - up frame 2 byte - mask 0 the bit 0 is the byte 1 mask of basic wake - up frame 2. --- the bit 31 is the byte 32 mask of basic wake - up frame 2. setting to 0, after power - on reset. d44/dbwf2bm1 basic wake - up frame 2 byte - mask 1 regist er bit attribute bit name description 31:0 r/w wf2bm1 basic wake - up frame 2 byte - mask 1 the bit 0 is the byte 33 mask of basic wake - up frame 2. --- the bit 31 is the byte 64 mask of basic wake - up frame 2. setting to 0, after power - on reset. d48/dbwf2bm2 basic wake - up frame 2 byte - mask 2 register bit attribute bit name description 31:0 r/w wf2bm2 basic wake - up frame 2 byte - mask 2 the bit 0 is the byte 65 mask of basic wake - up frame 2. --- the bit 31 is the byte 96 mask of basic wake - up frame 2. setting to 0, after power - on reset. d4c/dbwf2bm3 basic wake - up frame 2 byte - mask 3 register bit attribute bit name description 31:0 r/w wf2bm3 basic wake - up frame 2 byte - mask 3 the bit 0 is the byte 97 mask of basic wake - up frame 2. --- the bit 31 is the byte 12 8 mask of basic wake - up frame 2. setting to 0, after power - on reset.
w89c841f /d pub lication release date: october 1 8 , 2001 - 71 - revision a3 d50/dbwf3bm0 basic wake - up frame 3 byte - mask 0 register bit attribute bit name description 31:0 r/w wf3bm0 basic wake - up frame 3 byte - mask 0 the bit 0 is the byte 1 mask of basic wake - up frame 3. --- the bit 31 is the byte 32 mask of basic wake - up frame 3. setting to 0, after power - on reset. d54/dbwf3bm1 basic wake - up frame 3 byte - mask 1 register bit attribute bit name description 31:0 r/w wf3bm1 basic wake - up frame 3 byte - mask 1 the bit 0 is the byte 33 mask of basic wake - up frame 3. --- the bit 31 is the byte 64 mask of basic wake - up frame 3. setting to 0, after power - on reset. d58/dbwf3bm2 basic wake - up frame 3 byte - mask 2 register bit attribute bit name description 31:0 r/w wf3b m2 basic wake - up frame 3 byte - mask 2 the bit 0 is the byte 65 mask of basic wake - up frame 3. --- the bit 31 is the byte 96 mask of basic wake - up frame 3. setting to 0, after power - on reset. d5c/dbwf3bm3 basic wake - up frame 3 byte - mask 3 register bit attr ibute bit name description 31:0 r/w wf3bm3 basic wake - up frame 3 byte - mask 3 the bit 0 is the byte 97 mask of basic wake - up frame 3. --- the bit 31 is the byte 128 mask of basic wake - up frame 3. setting to 0, after power - on reset.
w 89c841f /d - 72 - d60/dbwf4bm0 basic w ake - up frame 4 byte - mask 0 register bit attribute bit name description 31:0 r/w wf4bm0 basic wake - up frame 4 byte - mask 0 the bit 0 is the byte 1 mask of basic wake - up frame 4. --- the bit 31 is the byte 32 mask of basic wake - up frame 4. setting to 0, aft er power - on reset. d64/dbwf4bm1 basic wake - up frame 4 byte - mask 1 register bit attribute bit name description 31:0 r/w wf4bm1 basic wake - up frame 4 byte - mask 1 the bit 0 is the byte 33 mask of basic wake - up frame 4. --- the bit 31 is the byte 64 mask of basic wake - up frame 4. setting to 0, after power - on reset. d68/dbwf4bm2 basic wake - up frame 4 byte - mask 2 register bit attribute bit name description 31:0 r/w wf4bm2 basic wake - up frame 4 byte - mask 2 the bit 0 is the byte 65 mask of basic wake - up frame 4. --- the bit 31 is the byte 96 mask of basic wake - up frame 4. setting to 0, after power - on reset. d6c/dbwf4bm3 basic wake - up frame 4 byte - mask 3 register bit attribute bit name description 31:0 r/w wf4bm3 basic wake - up frame 4 byte - mask 3 the bit 0 is the byte 97 mask of basic wake - up frame 4. --- the bit 31 is the byte 128 mask of basic wake - up frame 4. setting to 0, after power - on reset.
w89c841f /d pub lication release date: october 1 8 , 2001 - 73 - revision a3 dc0/dbrar boot rom access register the register is used to specify the control function and the data message p assing for the on board boot rom. bit attribute bit name description 31 r - reserved. fixed to 0. 30:28 r /w bromsel boot rom size select bromsel bits decides the size of the on board boot rom device. 00x = no boot rom 010 = 8k 011 = 16k 100 = 32k 101 = 64k 110 = 128k 111 = 256k loaded from eeprom after power - on reset. 27 r/w bromrd bootrom read control when eesel bit of register dc4/deear[31] is reset, setting this bit will perform the on - board boot rom read operation with the readi ng address specified by bits broma. the bit bromrd will be cleared automatically after bootrom read operation is completed. bit bromrd will not allow to be set high, even writing a logic 1 to bromrd if the bit eesel is set. 26 r/w bromwr bootrom write con trol when eesel bit of register dc4/deear[31] is reset, setting this bit will perform the on - board boot rom write operation with the writing address specified by broma. this bit bromwr will be cleared automatically after bootrom write operation is complete d. the bromwr will not allow to be set high, even writing a logic 1 to bromwr if the bit eesel is set. 25:8 r/w broma boot rom offset address this field contains boot rom offset address. 7:0 r/w bromd boot rom data bromd are used to store the read/write data for the on board boot rom access when eesel is reset to low. bromd is of no meaning if the eesel is set to high.
w 89c841f /d - 74 - dc4/deear eeprom access register the register is used to read or write information between system and eeprom. bit attribute bit name d escription 31 r/w eesel eeprom/bootrom select 1: eeprom access through dc4/deear is allowed. (default) 0: bootrom access through dc0/dbrar is allowed. 30 r/w starteerw start eeprom read/write access set to 1, to start eeprom rd/wr access. it will be cle ared to 0 automatically, after access is complete. 29:28 r/w ee r w eeprom read/write command 00: read 01: write 10: write protection disable 11: write protection enable 27:23 r ------- reserved. fixed to 0 22:16 r/w eeoa eeprom offset address this field contains eeprom offset address. 15:0 r/w eedata eeprom data eeprom data is used to store the read/write data for the on board eeprom access when eesel is set to high. eedata is of no meaning if the eesel is set to low. dc8/dmmar mii management access r egister the register is used to read or write information between system and mii management registers in transceiver. bit attribute bit name description 31 r/w startmdiorw start mdio read/write when set to 1, mdio starts to read/ write phy data. it will be clear automatically, when access completes. 30:29 r/w mdiorw mdio rd/wr command 01: write 10: read (default) 00, 11: reserved
w89c841f /d pub lication release date: october 1 8 , 2001 - 75 - revision a3 dc8/dmmar mii management access register, continued bit attribute bit name description 28:26 r ----- reserved. fixed to 0 25:21 r/w phyadd phy address the phy address must be the same as internal transceiver?s phy address setting. deafult to 01h. 20:16 r/w regadd phy?s register address refer to mii management registers to access the dedicated register. 15:0 r/w regdata phy register data phy register data is used to store the read/write data for mii management registers in embedded transceiver. dcc/dpa0 physical address register 0 the register defines the first 32 bits of the 48 bits mac address. the dpa0 value is loaded fro m eeprom after hardware reset bit attribute bit name description 31:24 r/w par3 physical address 3 the par3 defines the bit 24 - 31 of the mac address. 23:16 r/w par2 physical address 2 the par2 defines the bit 16 - 23 of the mac address. 15:8 r/w par1 physical address 1 the par1 defines the bit 8 - 15 of the mac address. 7:0 r/w par0 physical address 0 the par0 defines the bit 0 - 7 of the mac address. dd0/dpa1 physical address register 1 the register defines the last 16 bits of the 48 bits mac addre ss. the dpa1 value is loaded from eeprom after hardware reset bit attribute bit name description 31:16 r --- reserved. fixed at 0. 15:8 r/w par5 physical address 5 the par5 defines the 40 - 47 bit of the 48 bit of the mac address. 7:0 r/w par4 physical address 4 the par0 defines the 32 - 39 bit of the 48 bit of the mac address.
w 89c841f /d - 76 - ddc/drfctv rxdma flow control threshold value bit attribute bit name description 31:18 r --- reserved. fixed to 0. 17:9 r/w htv high threshold value when the receive byte count in the rx fifo is greater than high threshold value, a pause packet with max pause time will be transmitted if bit tfcen of register c1c/cncr is set. default value: 9?h180 8:0 r/w ltv low threshold value when the receive byte count in the rx fifo is less than low threshold value, a pause packet with min pause time will be transmitted if bit tfcen of register c1c/cncr is set. default value: 9?h100 df0/dfer function event register this register is used for reporting of interrupt pending and power - managemen t event detection in a cardbus system. a field in this register is set when the corresponding field in the function present state register changes its value. writing " 1 " into a field clear the field. writing " 0 " has no effect bit attribute bit name descrip tion 31:16 r --- reserved. fixed to 0. 15 r/wc intr i nterrupt event it is set when the interrupt is pending or frs_intr bit in the register dfc/dffer[15] is set, regardless the mask value. 14:5 r ---- reserved. fixed to 0. 4 sticky bit, r/wc gwake gene ral wake - up event it is set when the pre_gwake bit in register df8/dfpsr[4] changes its state from 0 to 1 or frs_gwake bit in the dfc/dffer[4] is set, regardless the mask value. this bit is cleared by write 1 and writing 0 has no effect. this bit is defau lt to 0 if pmeb generation from d3 cold is not supported. if pmeb generation from d3 cold is supported, then this bit is sticky and must be explicitly cleared by the operating system each time it is initially loaded. note: when w89c841f is configured into ca rdbus system, writing 1 to the field will clear this bit and the pme_status bit in the register fe0/fpmr1[15] too. or writing 1 to the pme_status bit in the register fe0/fpmr1[15] will clear pme_status bit and this gwake bit. 3:0 r --- reserved. fixed to 0.
w89c841f /d pub lication release date: october 1 8 , 2001 - 77 - revision a3 df4/dfemr function event mask register this register gives software the ability to control what events in the function cause the status changed interrupts or the host system wakeup. this register controls the assertion of the signals intab and cstschg in a cardbus system. bit attribute bit name description 31:16 r --- reserved. fixed to 0. 15 r/w intr_ en interrupt enable setting 1 enables the intr in the function event register to generate interrupt on the intab pin. 14 sticky bit, r/w wkup_ en w ake - up enable setting 1, enables the gwake bit in the register df0/dfer to generate the wakeup event on the cstschg line if the gwake_en field is set together. when this bit reset to 0, the wakeup function is disable. this bit defaults to 0 if pmeb generat ion from d3 cold is not supported. if pmeb generation from d3 cold is supported, then this bit is sticky and must be explicitly cleared by the operating system each time it is initially loaded. 13:5 r --- reserved. fixed to 0. 4 sticky bit, r/w gwake_ en g eneral wake - up enable setting 1, enables the gwake bit in the register df0/dfer to generate the wakeup event on the cstschg line if the wkup field is also set . when reset to 0, the wakeup function is disable. this bit defaults to 0 if pmeb generation fro m d3 cold is not supported. if pmeb generation from d3 cold is supported, then this bit is sticky and must be explicitly cleared by the operating system each time it is initially loaded. note: when w89c841f is configured into cardbus system, setting or cle aring pme_en bit in register fe0/fpmr1[8] will also setting or clearing gwake_en & wkup_en bits at the same time. bits gwake_en & wkup_en are allowed to be reset after setting pme_en bit. 3:0 r --- reserved. fixed to 0.
w 89c841f /d - 78 - df8/dfpsr function present s tate register this is read - only register reflects the current state of each condition that can cause a status change event. bit attribute bit name description 31:16 r ---- reserved. fixed to 0. 15 r pre_int present interrupt status it reflects the curre nt state of interrupt requests regardless of the mask value. it is set when the ethernet function has a pending interrupt and cleared when the software driver acknowledges all active interrupts from register c14/cisr. 14:5 r ---- reserved. fixed to 0. 4 r pre_ gwake present general wake - up status: it reflects the current state of the wake - up event. this bit is cleared when either the general wake - up event in the function event register is cleared, or when the pme_status bit in the register fe0/fpmr1[15] is cleared. 3:0 r ---- reserved. fixed to 0. dfc/dffer function force event register this register is used to generate interrupt or wake - up event. bit attribute bit name description 31:16 r --- reserved. fixed to 0. 15 w frs_intr force interrupt even t: writing 1 to this field sets the intr bit in the register df0/dfer. pre_intr bit in the register df8/dfpsr[15] is not affected and continues to reflect the current state of the functional interrupt. writing 0 has no effect. 14:5 r --- reserved. fixed t o 0. 4 w frs_ gwake force general wake - up event: writing 1 to this field sets the gwake bit in the register df0/dfer. pre_gwake bit in the register df8/dfpsr[4] is not affected and continues to reflect the current state of the wakeup request. writing 0 h as no effect. 3:0 r --- reserved. fixed to 0.
w89c841f /d pub lication release date: october 1 8 , 2001 - 79 - revision a3 mii management registers w89c841f supports mdc/mdio interface to access mii management registers located in embedded phyceiver. the following table list all of the mii management registers supported by w89c 841f. address register name default 0 0h control register 3 1 00 h 0 1h status register 7849 h 0 2h phy identifier register 1 0022h 03h phy identifier register 2 e011h 0 4h auto negotiation advertisement register 05e1h 0 5h auto negotiation link partner abil ity register 01e1 h 0 6h auto negotiation expansion register 0004 h 0 7h next page transmit register 2001 h 0 8h link partner next page register 0000 h 0 9h ? 0 fh ieee reserved ffff h 10h phy specific control register 0680 h 11h port configuration register 002 6h 12h phy specific status register 000f h 13h global interrupt enable register 0000 h 14h global interrupt status register 0000 h 15h receive error counter 0000 h
w 89c841f /d - 80 - control (register 0h) bit(s) name description r/w default 0.15 rst reset 1 ? phy reset 0 ? normal operation r/w sc 0h 0.14 lpbk loop back enable 1 ? enable loopback mode 0 ? disable loopback mode r/w 0h 0.13 speed_lsb speed selection lsb 0.13 0 0 10 mbits/s 0 1 100 mbits/s 1 0 1000 mbits/s 1 1 reserved r/w 1h 0.12 anen auto negotiation enable 1 ? enable auto negotiation process 0 ? disable auto negotiation process r/w 1h 0.11 pdn power down enable 1 ? power down 0 ? normal operation r/w 0h 0.10 iso isolate ad2105 from network 1 ? isolate phy from mii/rmii 0 ? normal operation r/w 0h 0.9 anen_ rst restart auto negotiation 1 ? restart auto negotiation process 0 ? normal operation r/w sc 0h 0.8 dplx duplex mode 1 ? full duplex mode 0 ? half duplex mode r/w 1h 0.7 coltst collision test 1 ? enable col signal test 0 ? disable col signal test r/w 0h 0.6 speed_msb speed selection msb ro 0h 0.5:0 reserved not used ro 00h
w89c841f /d pub lication release date: october 1 8 , 2001 - 81 - revision a3 status (register 1h) bit(s) name description r/w default 1.15 cap_t4 100base - t4 capable ro 0h 1.14 cap_txf 100base - x full duplex capable ro 1h 1.13 cap_txh 100base - x half duplex capable ro 1h 1.12 cap_tf 10m full duplex capable ro 1h 1.11 cap_th 10m half duplex capable ro 1h 1.10 cap_t2 100base - t2 capable ro 0h 1.9:7 reserved ignored when read ro 0h 1.6 cap_supr mf preamble suppression c apable ro 1h 1.5 an_comp auto negotiation complete 1 ? auto negotiation process completed 0 ? auto negotiation process not completed ro 0h 1.4 rem_flt remote fault detect 1 ? remote fault detected 0 ? remote fault not detected ro 0h 1.3 cap_aneg auto ne gotiation ability 1 ? capable of auto negotiation 0 ? not capable of auto negotiation ro 1h 1.2 link link status 1 ? link is up 0 ? link is down ro, ll 0h 1.1 jab jabber detect 1 ? jabber condition detected 0 ? jabber condition not detected ro, lh 0h 1 .0 extreg extended capability 1 ? extended register set 0 ? no extended register set ro 1h phy identifier register (register 2h) bit(s) name description r/w default 2.15:0 phy - id[15:0] ieee address ro 0022 phy identifier register (register 3h) bit(s) na me description r/w default 315:0 phy - id[15:0] ieee address/model no./rev. no. ro e011
w 89c841f /d - 82 - advertisement (register 4h) bit(s) name description r/w default 4.15 np next page ro 0h 4.14 reserved reserved ro 0h 4.13 rf remote fault 1 ? remote fault has been d etected 0 ? no remote fault has been detected r/w 0h 4.12 ieee reserved reserved ro 0h 4.11 asm_dir asymmetric pause direction. bit[11:10] capability 00 no pause 01 symmetric pause asymmetric pause toward link partner both symmetric pause and asymmetric pause toward local device r/w 0h 4.10 pause pause operation for full duplex r/w 1h 4.9 t4 technology ability for 100base - t4 ro 0h 4.8 tx_fdx 100base - tx full duplex 1 ? capable of 100m full duplex operation 0 ? not capable of 100m full duplex operation r/w 1h 4.7 tx_hdx 100base - tx half duplex 1 ? capable of 100m operation 0 ? not capable of 100m operation r/w 1h 4.6 10_fdx 10base - t full duplex 1 ? capable of 10m full duplex operation 0 ? not capable of 10m full duplex operation r/w 1h 4.5 10 _hdx 10base - t half duplex 1 ? capable of 10m operation 0 ? not capable of 10m operation r/w 1h 4.4:0 selector field these 5 bits are hardwired to 00001b. ro 01h auto negotiation link partner ability (register 5h) bit(s) name description r/w default 5.15 npage next page 1 ? capable of next page function 0 ? not capable of next page function ro 0h 5.14 ack acknowledge 1 ? link partner acknowledges reception of the ability data word 0 ? not acknowledged ro 0h 5.13 rf remote fault 1 ? remote fault has been detected 0 ? no remote fault has been detected ro 0h 5.12:11 ieee reserved reserved ro 0h
w89c841f /d pub lication release date: october 1 8 , 2001 - 83 - revision a3 auto negotiation link partner ability (register 5h) , continued bit(s) name description r/w default 5.11 lp_dir link partner asymmetric pause direction. ro 0h 5. 10 lp_pau link partner pause capability ro 0h 5.9 lp_t4 link partner technology ability for 100base - t4 ro 0h 5.8 lp_fdx 100base - tx full duplex 1 ? capable of 100m full duplex operation 0 ? not capable of 100m full duplex operation ro 1h 5.7 lp_hdx 100ba se - tx half duplex 1 ? capable of 100m operation 0 ? not capable of 100m operation ro 1h 5.6 lp_f10 10base - t full duplex 1 ? capable of 10m full duplex operation 0 ? not capable of 10m full duplex operation ro 1h 5.5 lp_h10 10base - t half duplex 1 ? capabl e of 10m operation 0 ? not capable of 10m operation ro 1h 5.4:0 selector field encoding definitions. ro 1h auto negotiation expansion register (register 6h) bit(s) name description r/w default 6.15:5 reserved reserved ro 000h 6.4 pfault parallel detect ion fault 1 ? fault has been detected 0 ? no fault detect ro, lh 0h 6.3 lpnpable link partner next page able 1 ? link partner is next page capable 0 ? link partner is not next page capable ro 0h 6.2 npable next page able defaults to 1, indicating ad2105 is next page able. ro 1h 6.1 pgrcv page received 1 ? a new page has been received 0 ? no new page has been received ro, lh 0h 6.0 lpanable link partner auto negotiation able 1 ? link partner is auto negotiable 0 ? link partner is not auto negotiable ro 0 h
w 89c841f /d - 84 - next page transmit register (register 7h) bit(s) name description r/w default 7.15 tnpage transmit next page transmit code word bit 15 r/w 0h 7.14 reserved reserved transmit code word bit 14 ro 0h 7.13 tmsg transmit message page transmit code word bi t 13 r/w 1h 7.12 tack2 transmit acknowledge 2 transmit code word bit 12 r/w 0h 7.11 ttog transmit toggle transmit code word bit 11 ro 0h 7.10:0 tfld[10:0] transmit message field transmit code word bit 10. . .0 r/w 001h link partner next page register (r egister 8h) bit(s) name description r/w default 8.15 pnpage link partner next page receive code word bit 15 ro 0h 8.14 pack link partner acknowledge receive code word bit 14 ro 0h 8.13 pmsgp link partner message page receive code word bit 13 ro 0h 8.12 pack2 link partner acknowledge 2 receive code word bit 12 ro 0h 8.11 ptog link partner toggle receive code word bit 11 ro 0h 8.10:0 pfld[10:0] link partner message field receive code word bit 11 ro 000h
w89c841f /d pub lication release date: october 1 8 , 2001 - 85 - revision a3 channel and 10m configuration register (registe r 10h) bit(s) name description r/w default 16. 15:12 reserved reserved ro 0h 16.11 ifsel interface select. 0: mii 1: rmii ro 0h 16.10 enreg8 enable register 8 to store next page information. 1 ? store next page in register 8 0 ? store next page in regis ter 5 r/w 1h 16.9 xoven cross over auto detect enable. 0: disable 1: enable r/w 1 h 16.8 dispmg disable power management feature. 0: enable 1: disable r/w 0h 16.7 enrjab enable receive jabber monitor. 0: disable 1: enable r/w 1h 16.6:5 vthr[1:0] mediu m detect voltage control (peak to peak) 00: 50 mv 01: 100 mv 10: 150 mv 11: 200 mv r/w 0h 16.4 drv62ma reduce 10m driver to 62ma 1 = 62 ma 0 = normal r/w 0h 16.3 apdis auto polarity disable 1 = auto polarity function disabled 0 = normal r/w 0h 16.2 dist jab disable transmit jabber 1 ? disable transmit jabber function 0 ? enable transmit jabber function r/w 0h 16.1 eth enable extended distance 1 ? lower 10base - t receive threshold 0 ? normal 10base - t receive threshold r/w 0h 16.0 fgdlnk force 10m receive good link 1 ? force good link 0 ? normal operation r/w 0h
w 89c841f /d - 86 - phy 100m module control register (register 11h) bit(s) name description r/w default 17. 15:8 reserved reserved ro 0h 17.7 selfx fiber select 1: fiber mode 0: tp mode r/w 0h 17.6:5 fxtsel[1:0] fi ber control signal r/w 1h 17.4 disscr disable scrambler 1 ? disable scrambler 0 ? enable scrambler r/w 0h 17.3 enfefi enable fefi 1 ? enable fefi 0 ? disable fefi r/w pin 17.2:1 bslimt[1:0] base line threshold adjust r/w 1h 17.0 adfs ad full scale adju st r/w 0 h phy specific status register (register 12h) bit(s) name description r/w default 18. 15:13 reserved reserved ro 0h 18.12 fxen fiber enable. only changed when phy reset 0: tx 1: fx mode or ? ed result of pi_selfx and 17.9 (selfx) ro pin 18.11 xov er cross over. 0: mdi mode 1: mdix mode ro 0h 18.10 jab real time jabber status 1 ? jabber 0 ? no jabber ro 0h 18.9 polar polarity. 0: normal polarity 1: polarity reversed ro 0h
w89c841f /d pub lication release date: october 1 8 , 2001 - 87 - revision a3 phy specific status register (register 12h) , continued bit(s) name descr iption r/w default 18.8 pauout pause out capability. disabled when half duplex. 0: lack of pause out capability 1: has pause out capability ro 0h 18.7 pauin pause in capability. disabled when half duplex. 0: lack of pause in capability 1: has pause in ca pability ro 0h 18.6 duplex operating duplex 1 ? full duplex 0 ? half duplex ro 0 h 18.5 speed operating speed 1 ? 100 mb/s 0 ? 10 mb/s ro 0h 18.4 link real time link status 1 ? link up 0 ? link down ro 0h 18.3 recpau pause recommend value. only changed wh en phy reset. this bit is disabled automatically when recdup is 0. 0: pause disable 1: pause enable ro 1h 18.2 recdup duplex recommended value. only changed when phy reset 1: full duplex 0: half duplex ro 1h 18.1 recspd speed recommend value. only chang ed when phy reset 1: 100m 0: 10m ro 1h 18.0 recanen recommended auto negotiation value. only changed when phy reset ro 1h
w 89c841f /d - 88 - interrupt enable register (register 13h) bit(s) name description r/w default 19.15 xovchg cross over mode changed interrupt enabl e 1 ? interrupt enable 0 ? interrupt disable r/w 0h 19.14 spdchg speed changed interrupt enable 1 ? interrupt enable 0 ? interrupt disable r/w 0h 19.13 dupchg duplex changed interrupt enable 1 ? interrupt enable 0 ? interrupt disable r/w 0h 19.12 pgrchg page received interrupt enable 1 ? interrupt enable 0 ? interrupt disable r/w 0h 19.11 lnkchg link status changed interrupt enable 1 ? interrupt enable 0 ? interrupt disable r/w 0h 19.10 symerr symbol error interrupt enable 1 ? interrupt enable 0 ? inte rrupt disable r/w 0h 19.9 fcar false carrier interrupt enable 1 ? interrupt enable 0 ? interrupt disable r/w 0h 19.8 fourun fifo over/underrun interrupt enable 1 ? interrupt enable 0 ? interrupt disable r/w 0h 19.7 jabint jabber interrupt enable 1 ? int errupt enable 0 ? interrupt disable r/w 0h 19.6:0 reserved reserved ro 00h
w89c841f /d pub lication release date: october 1 8 , 2001 - 89 - revision a3 interrupt status register (register 14h) bit(s) name description r/w default 20.15 xovchg cross over mode changed 1 ? cross over mode changed 0 ? cross over mode not changed co r 0h 20.14 spdchg speed changed 1 ? speed changed 0 ? speed not changed cor 0h 20.13 dupchg duplex changed 1 ? duplex changed 0 ? duplex not changed cor 0h 20.12 pgrchg page received 1 ? page received 0 ? page not received cor 0h 20.11 lnkchg link stat us changed 1 ? link status changed 0 ? link status not changed cor 0h 20.10 symerr symbol error 1 ? symbol error 0 ? no symbol error cor 0h 20.9 fcar false carrier 1 ? false carrier 0 ? no false carrier will be high whenever link is failed. cor 0h 20.8 fourun fifo over/underrun 1 ? fifo over/uner run 0 ? no fifo over/under run cor 0h 20.7 jabint jabber 1 ? jabber 0 ? no jabber cor 0h 20.6:0 reserved reserved cor 00h receive error counter register (register 15h) bit(s) name description r/w default 21. 15:0 erb[15:0] error counter. includes false carrier jabber symbol error fifo under/over run link code word error error start of stream error end of stream ro 0000h
w 89c841f /d - 90 - 10. electrical chara cteristics absolute maximum ratings parameter symbol min. max. unit operating temperature t a 0 70 c storage temperature t s - 55 125 c supply voltage v cc_core v cc_io 2.25 3.0 2.75 3.6 v input voltage v in v ss 5 + 0.5 v output voltage v out v ss 3.6 v power supply (t a = 0 c to 70 c) parameter symbol condition max. uni t power supply current (d0 state) idd0 v cc_core = 2.5v v cc_io = 3.3v 210 ma power supply current (d1) idd1 v cc_core = 2.5v v cc_io = 3.3v 178 ma power supply current (d3 hot) idd1 v cc_core = 2.5v v cc_io = 3.3v 178 ma power supply current (d3 cold) idd1 v cc_core = 2.5v v cc_io = 3.3v 158 ma dc characteristics (v cc_core = 2.25v to 2.75v, v cc = 3.0v to 3.6v, v ss = 0v, t a = 0 c to 70 c) parameter symbol condition min. max. unit input low voltage v il 0.7 v input high voltage v ih 1.7 v output low volt age v ol i ol = 4.0 ma 0 0.4 v output high voltage v oh i oh = - 4.0 ma 1.85 3.6 v input low current i il v in = v cc - 10 10 m a input high current i ih v in = 0v - 10 10 m a
w89c841f /d pub lication release date: october 1 8 , 2001 - 91 - revision a3 ac characteristics (v cc_core = 2.5v, v cc_io = 3.3v, v ss = 0 v, t a = 0 c to 70 c) pci s lave read transaction 1 2 3 0 clk ad[31::0] address data be#'s bus cmd devsel# trdy# irdy# c/be[3:0]# frame# t9 t11 t12 t13 t10 par t7 input output t2 t3 t5 t8 t1 t4 t6 t14 t15 idsel# parameters symbol min. typ. max. unit pci input signal set - up time* t1 7 ns pci input signal hold time* t2 2 ns be byte enable set - up time t3 7 ns be byte enable hold time t4 2 ns irdy# set - up time t5 7 ns irdy# hold time t6 2 ns par input set - up time t7 7 ns par input hold time t8 2 ns devsel# driven time t9 9 10 11 ns devsel# hold time t10 9 10 11 ns output data hold time t11 9 10 11 ns trdy# driven time t12 9 10 11 ns trdy# hold time t13 9 10 11 ns par output driven time t14 9 10 11 ns par output hold time t15 9 10 11 ns note: address, command, and frame# for slave access, idsel# for configuration read transaction
w 89c841f /d - 92 - ac characteristics, continued pci slave write transa ction clk ad[31::0] address data be#'s 1 2 3 bus cmd devsel# trdy# irdy# c/be[3:0]# frame# t9 t11 t12 t13 t14 t10 par t7 input input t1 t2 t3 t5 t8 t15 t4 t6 t16 idsel# perr# t17 t18 0 data parameters symbol min. typ. max. unit pci input signal set - up time* t1 7 ns pci input signal hold time* t2 2 ns be byte enable set - up time t3 7 ns be byte enable hold time t4 2 ns irdy# set - up time t5 7 ns irdy# hold time t6 2 ns par input set - up time t7 7 ns par input hold time t8 2 ns devsel# driven time t9 9 10 11 ns devsel# hold time t10 9 10 11 ns input data set - up time t11 7 ns input data hold time t12 2 ns trdy# driven time t13 9 10 11 ns trdy# hold time t14 9 10 11 ns par input set - up time t15 7 ns par input hold time t16 2 ns perr# driven time** t17 9 10 11 ns perr# hold time** t18 9 10 11 ns note: address, command, and frame# for slave access, idsel# for configura tion read transaction **perr# will be asserted if the parity error event occurred.
w89c841f /d pub lication release date: october 1 8 , 2001 - 93 - revision a3 ac characteristics, continued pci transaction, termination disconnect - c/retry type clk frame# ad[31::0] irdy# trdy# address bus cmd be#'s 1 2 3 4 15 16 17 c/be[3::0]# 0 t1 18 19 t3 stop# devsel# t2 parameters symbol min. typical max. unit frame# deasserted from clock 15 t1 2 ns clock 16 to stop# asserted time t2 9 10 11 ns clock 18 to stop# and devsel# hold time t3 9 10 11 ns notes: 1) the other timing requirements for pci input signal are as the read transaction timing. 2) t1, t2 and t3 are used for the disconnect type c (host try to transfer more than one data phase).
w 89c841f /d - 94 - ac characteristics, continued target - abort type address bus cmd be#'s 1 2 3 4 5 6 7 0 t1 t2 t3 clk frame# ad[31::0] irdy# trdy# c/be[3::0]# stop# devsel# 8 9 parameters symbol min. typical max. unit frame# deasserted from clock 15 t1 2 ns clock 4 to devsel# hold time t2 9 10 11 ns clock 6 to stop# hold t ime t3 9 10 11 ns notes: 1) the other timing requirements for pci input signal are as the read transaction timing. 2) t2 and t3 are used for the target abort type (host addressing error).
w89c841f /d pub lication release date: october 1 8 , 2001 - 95 - revision a3 ac characteristics, continued boot rom read cycle timing parameters symbol min. max. unit read cycle time t rc 330 ns data set - up time t s 5 - ns data hold time t h 2 - ns t rc t s data valid v ih t h btadd[17:0] btcsb btoeb btweb btdata[7 :0]
w 89c841f /d - 96 - ac characteristics, continued boot rom write cycle timing parameters symbol min. max. unit address set - up time t as - 150 ns address hold time t ah - 60 ns btweb and btcsb set - up time t cs 88 ns btcsb pulse width t cp - 120 ns btweb pulse width t wp - 600 ns data set - up time t ds - 1 20 ns t as t ah t cs t wp t cp v ih data valid t ds btadd[17:0] btcsb btweb btoeb btdata[7:0]
w89c841f /d pub lication release date: october 1 8 , 2001 - 97 - revision a3 ac characteristics, continued serial eeprom timing t2 t1 t5 eecs t6 t8 t3 t7 t4 eeck eedo eedi parameters symbol typ. unit eecs asserted to eeck t1 610 ns eecs hold from eeck t2 3 ns eeck off time t3 600 ns eeck on time t4 600 ns eeck clock period t5 1 .2 us eedi set - up time t6 600 ns eedi hold time t7 600 ns eedo output delay t8 100 ns
w 89c841f /d - 98 - ac characteristics, continued phyceiver mii timing parameters symbol typ. unit output delay for rxd, rx_dv, rx_er t1 5 ns set - up time for txd, tx_en, tx_er t2 15 ns hold time for txd, tx_en, tx_er t3 0 ns clock cycle (100m) (10m) t4 40 400 ns rx_clk rxd[3:0], rx_dv, rx_er t1 tx_clk txd[3:0], tx_en, tx_er t2 t3 t4
w89c841f /d pub lication release date: october 1 8 , 2001 - 99 - revision a3 ac characteristics, continued mac controller mii timing parameters symbol typ. unit output delay for txd, tx_en, tx_er t1 7 ns setup time for rxd, rx_dv, rx_er t2 10 ns hold time for rxd, rx_dv, rx_er t3 10 ns clock cycle (100m) (10m) t4 40 400 ns tx_clk txd[3:0], tx_en, tx_er t1 rx_clk rxd[3:0], rx_dv, rx_er t2 t3 t4
w 89c841f /d - 100 - 11. package dimensio ns w89c841f: 128l qfp ( 14 x 20 x 2.75 mm footprint 3.2 mm) 0.10 0 12 0 0.004 1.60 1.00 17.40 0.80 17.20 0.60 17.00 0.063 0.039 0.685 0.031 0.677 0.023 0.669 0.50 14.10 0.25 0.25 2.87 3.40 14.00 2.72 13.90 0.10 0.15 2.57 0.10 0.555 0.010 0.010 0.113 0.134 0.551 0.107 0.020 0.547 0.004 0.006 0.101 0.004 symbol min. nom. max. max. nom. min. dimension in inch dimension in mm a b c d e h d h e l y a a l 1 1 2 e 0.008 0.006 0.15 0.20 12 0.783 0.787 0.791 19.90 20.00 20.10 0.905 0.913 0.921 23.00 23.20 23.40 0.055 0.071 1.40 1.80 103 128 102 65 64 39 38 1 c detail f see detail f 1 l l seating plane 1 a a y e h e d d h b e a 2 q
w89c841f /d pub lication release date: october 1 8 , 2001 - 101 - revision a3 package dimensions, continued W89C841D: 128l lqfp (14 x 20 x 1.4 mm) 103 128 102 65 64 39 38 1 c detail f see detail f 1 l l seating plane 1 a a y e h e b e d d h a 2 0.10 0 12 0 0.004 1.00 0.75 16.10 0.60 16.00 0.45 15.90 0.039 0.030 0.634 0.024 0.630 0.018 0.626 0.50 14.10 0.25 0.27 1.45 1.60 14.00 1.40 13.90 0.10 0.15 1.35 0.05 0.555 0.010 0.011 0.057 0.063 0.551 0.055 0.020 0.547 0.004 0.006 0.053 0.002 symbol min. nom. max. max. nom. min. dimension in inch dimension in mm a b c d e h d h e l y a a l 1 1 2 e 0.008 0.006 0.15 0.20 12 0.783 0.787 0.791 19.90 20.00 20.10 0.862 0.866 0.870 21.90 22.00 22.10 q
w 89c841f /d - 102 - headquarters no. 4, creation rd. iii, science-based industrial park, hsinchu, taiwan tel: 886-3-5770066 fax: 886-3-5665577 http://www.winbond.com.tw/ taipei office 11f, no. 115, sec. 3, taipei, taiwan tel: 886-2-27190505 fax: 886-2-27197502 winbond electronics corporation america 2727 north first street, san jose, ca 95134, u.s.a. tel: 1-408-9436666 fax: 1-408-5441798 winbond electronics (h.k.) ltd. no. 378 kwun tong rd., kowloon, hong kong fax: 852-27552064 unit 9-15, 22f, millennium city, tel: 852-27513100 please note that all data and specifications are subject to change without notice. all the trade marks of products and companies mentioned in this data sheet belong to their respective owners. winbond electronics (shanghai) ltd. 200336 china fax: 86-21-62365998 27f, 2299 yan an w. rd. shanghai, tel: 86-21-62365999 winbond electronics corporation japan shinyokohama kohoku-ku, yokohama, 222-0033 fax: 81-45-4781800 7f daini-ueno bldg, 3-7-18 tel: 81-45-4781881 min-sheng east. rd.,

▲Up To Search▲

Price & Availability of W89C841D

	To Download W89C841D Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .